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0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: Tegra194 on chip generic hardware timestamping engine (HTE)
0008 
0009 maintainers:
0010   - Dipen Patel <dipenp@nvidia.com>
0011 
0012 description:
0013   Tegra SoC has two instances of generic hardware timestamping engines (GTE)
0014   known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip
0015   IRQ lines for the state change respectively, upon detection it will record
0016   timestamp (taken from system counter) in its internal hardware FIFO. It has
0017   a bitmap array arranged in 32bit slices where each bit represent signal/line
0018   to enable or disable for the hardware timestamping. The GTE GPIO monitors
0019   GPIO lines from the AON (always on) GPIO controller.
0020 
0021 properties:
0022   compatible:
0023     enum:
0024       - nvidia,tegra194-gte-aon
0025       - nvidia,tegra194-gte-lic
0026 
0027   reg:
0028     maxItems: 1
0029 
0030   interrupts:
0031     maxItems: 1
0032 
0033   nvidia,int-threshold:
0034     $ref: /schemas/types.yaml#/definitions/uint32
0035     description:
0036       HTE device generates its interrupt based on this u32 FIFO threshold
0037       value. The recommended value is 1.
0038     minimum: 1
0039     maximum: 256
0040 
0041   nvidia,slices:
0042     $ref: /schemas/types.yaml#/definitions/uint32
0043     description:
0044       HTE lines are arranged in 32 bit slice where each bit represents different
0045       line/signal that it can enable/configure for the timestamp. It is u32
0046       property and depends on the HTE instance in the chip. The value 3 is for
0047       GPIO GTE and 11 for IRQ GTE.
0048     enum: [3, 11]
0049 
0050   '#timestamp-cells':
0051     description:
0052       This represents number of line id arguments as specified by the
0053       consumers. For the GTE IRQ, this is IRQ number as mentioned in the
0054       SoC technical reference manual. For the GTE GPIO, its value is same as
0055       mentioned in the nvidia GPIO device tree binding document.
0056     const: 1
0057 
0058 required:
0059   - compatible
0060   - reg
0061   - interrupts
0062   - nvidia,slices
0063   - "#timestamp-cells"
0064 
0065 additionalProperties: false
0066 
0067 examples:
0068   - |
0069     tegra_hte_aon: timestamp@c1e0000 {
0070               compatible = "nvidia,tegra194-gte-aon";
0071               reg = <0xc1e0000 0x10000>;
0072               interrupts = <0 13 0x4>;
0073               nvidia,int-threshold = <1>;
0074               nvidia,slices = <3>;
0075               #timestamp-cells = <1>;
0076     };
0077 
0078   - |
0079     tegra_hte_lic: timestamp@3aa0000 {
0080               compatible = "nvidia,tegra194-gte-lic";
0081               reg = <0x3aa0000 0x10000>;
0082               interrupts = <0 11 0x4>;
0083               nvidia,int-threshold = <1>;
0084               nvidia,slices = <11>;
0085               #timestamp-cells = <1>;
0086     };
0087 
0088 ...