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OSCL-LXR

 
 

    


0001 Synopsys ARC Local Timer with Interrupt Capabilities
0002 - Found on all ARC CPUs (ARC700/ARCHS)
0003 - Can be optionally programmed to interrupt on Limit
0004 - Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
0005   TIMER0 used as clockevent provider (true for all ARC cores)
0006   TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
0007 
0008 Required properties:
0009 
0010 - compatible : should be "snps,arc-timer"
0011 - interrupts : single Interrupt going into parent intc
0012                (16 for ARCHS cores, 3 for ARC700 cores)
0013 - clocks     : phandle to the source clock
0014 
0015 Example:
0016 
0017         timer0 {
0018                 compatible = "snps,arc-timer";
0019                 interrupts = <3>;
0020                 interrupt-parent = <&core_intc>;
0021                 clocks = <&core_clk>;
0022         };
0023 
0024         timer1 {
0025                 compatible = "snps,arc-timer";
0026                 clocks = <&core_clk>;
0027         };