0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung Exynos SoC Multi Core Timer (MCT)
0008
0009 maintainers:
0010 - Krzysztof Kozlowski <krzk@kernel.org>
0011
0012 description: |+
0013 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
0014 global timer and CPU local timers. The global timer is a 64-bit free running
0015 up-counter and can generate 4 interrupts when the counter reaches one of the
0016 four preset counter values. The CPU local timers are 32-bit free running
0017 down-counters and generate an interrupt when the counter expires. There is
0018 one CPU local timer instantiated in MCT for every CPU in the system.
0019
0020 properties:
0021 compatible:
0022 oneOf:
0023 - enum:
0024 - samsung,exynos4210-mct
0025 - samsung,exynos4412-mct
0026 - items:
0027 - enum:
0028 - samsung,exynos3250-mct
0029 - samsung,exynos5250-mct
0030 - samsung,exynos5260-mct
0031 - samsung,exynos5420-mct
0032 - samsung,exynos5433-mct
0033 - samsung,exynos850-mct
0034 - tesla,fsd-mct
0035 - const: samsung,exynos4210-mct
0036
0037 clocks:
0038 maxItems: 2
0039
0040 clock-names:
0041 items:
0042 - const: fin_pll
0043 - const: mct
0044
0045 reg:
0046 maxItems: 1
0047
0048 interrupts:
0049 description: |
0050 Interrupts should be put in specific order. This is, the local timer
0051 interrupts should be specified after the four global timer interrupts
0052 have been specified:
0053 0: Global Timer Interrupt 0
0054 1: Global Timer Interrupt 1
0055 2: Global Timer Interrupt 2
0056 3: Global Timer Interrupt 3
0057 4: Local Timer Interrupt 0
0058 5: Local Timer Interrupt 1
0059 6: ..
0060 7: ..
0061 i: Local Timer Interrupt n
0062 For MCT block that uses a per-processor interrupt for local timers, such
0063 as ones compatible with "samsung,exynos4412-mct", only one local timer
0064 interrupt might be specified, meaning that all local timers use the same
0065 per processor interrupt.
0066 minItems: 5 # 4 Global + 1 local
0067 maxItems: 20 # 4 Global + 16 local
0068
0069 required:
0070 - compatible
0071 - clock-names
0072 - clocks
0073 - interrupts
0074 - reg
0075
0076 allOf:
0077 - if:
0078 properties:
0079 compatible:
0080 contains:
0081 const: samsung,exynos3250-mct
0082 then:
0083 properties:
0084 interrupts:
0085 minItems: 8
0086 maxItems: 8
0087
0088 - if:
0089 properties:
0090 compatible:
0091 contains:
0092 const: samsung,exynos5250-mct
0093 then:
0094 properties:
0095 interrupts:
0096 minItems: 6
0097 maxItems: 6
0098
0099 - if:
0100 properties:
0101 compatible:
0102 contains:
0103 enum:
0104 - samsung,exynos5260-mct
0105 - samsung,exynos5420-mct
0106 - samsung,exynos5433-mct
0107 - samsung,exynos850-mct
0108 then:
0109 properties:
0110 interrupts:
0111 minItems: 12
0112 maxItems: 12
0113
0114 - if:
0115 properties:
0116 compatible:
0117 contains:
0118 enum:
0119 - tesla,fsd-mct
0120 then:
0121 properties:
0122 interrupts:
0123 minItems: 16
0124 maxItems: 16
0125
0126 additionalProperties: false
0127
0128 examples:
0129 - |
0130 // In this example, the IP contains two local timers, using separate
0131 // interrupts, so two local timer interrupts have been specified,
0132 // in addition to four global timer interrupts.
0133 #include <dt-bindings/clock/exynos4.h>
0134 #include <dt-bindings/interrupt-controller/arm-gic.h>
0135
0136 timer@10050000 {
0137 compatible = "samsung,exynos4210-mct";
0138 reg = <0x10050000 0x800>;
0139 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
0140 clock-names = "fin_pll", "mct";
0141
0142 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0143 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
0144 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0145 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
0146 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0147 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0148 };
0149
0150 - |
0151 // In this example, the timer interrupts are connected to two separate
0152 // interrupt controllers. Hence, an interrupts-extended is needed.
0153 #include <dt-bindings/clock/exynos4.h>
0154 #include <dt-bindings/interrupt-controller/arm-gic.h>
0155
0156 timer@101c0000 {
0157 compatible = "samsung,exynos4210-mct";
0158 reg = <0x101C0000 0x800>;
0159 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
0160 clock-names = "fin_pll", "mct";
0161
0162 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0163 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
0164 <&combiner 12 6>,
0165 <&combiner 12 7>,
0166 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0167 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0168 };
0169
0170 - |
0171 // In this example, the IP contains four local timers, but using
0172 // a per-processor interrupt to handle them. Only one first local
0173 // interrupt is specified.
0174 #include <dt-bindings/clock/exynos4.h>
0175 #include <dt-bindings/interrupt-controller/arm-gic.h>
0176
0177 timer@10050000 {
0178 compatible = "samsung,exynos4412-mct";
0179 reg = <0x10050000 0x800>;
0180 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
0181 clock-names = "fin_pll", "mct";
0182
0183 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0184 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
0185 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0186 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
0187 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
0188 };
0189
0190 - |
0191 // In this example, the IP contains four local timers, but using
0192 // a per-processor interrupt to handle them. All the local timer
0193 // interrupts are specified.
0194 #include <dt-bindings/clock/exynos4.h>
0195 #include <dt-bindings/interrupt-controller/arm-gic.h>
0196
0197 timer@10050000 {
0198 compatible = "samsung,exynos4412-mct";
0199 reg = <0x10050000 0x800>;
0200 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
0201 clock-names = "fin_pll", "mct";
0202
0203 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0204 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
0205 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0206 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
0207 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
0208 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
0209 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
0210 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
0211 };
