0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: NVIDIA Tegra186 timer
0008
0009 maintainers:
0010 - Thierry Reding <treding@nvidia.com>
0011
0012 description: >
0013 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
0014 counter. Each NV timer selects its timing reference signal from the 1 MHz
0015 reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
0016 programmed to generate one-shot, periodic, or watchdog interrupts.
0017
0018
0019 properties:
0020 compatible:
0021 oneOf:
0022 - const: nvidia,tegra186-timer
0023 description: >
0024 The Tegra186 timer provides ten 29-bit timer counters.
0025 - const: nvidia,tegra234-timer
0026 description: >
0027 The Tegra234 timer provides sixteen 29-bit timer counters.
0028
0029 reg:
0030 maxItems: 1
0031
0032 interrupts: true
0033
0034 allOf:
0035 - if:
0036 properties:
0037 compatible:
0038 contains:
0039 const: nvidia,tegra186-timer
0040 then:
0041 properties:
0042 interrupts:
0043 maxItems: 10
0044 description: >
0045 One per each timer channels 0 through 9.
0046
0047 - if:
0048 properties:
0049 compatible:
0050 contains:
0051 const: nvidia,tegra234-timer
0052 then:
0053 properties:
0054 interrupts:
0055 maxItems: 16
0056 description: >
0057 One per each timer channels 0 through 15.
0058
0059 required:
0060 - compatible
0061 - reg
0062 - interrupts
0063
0064 additionalProperties: false
0065
0066 examples:
0067 - |
0068 #include <dt-bindings/interrupt-controller/arm-gic.h>
0069 #include <dt-bindings/interrupt-controller/irq.h>
0070
0071 timer@3010000 {
0072 compatible = "nvidia,tegra186-timer";
0073 reg = <0x03010000 0x000e0000>;
0074 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0075 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0076 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0077 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0078 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0079 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0080 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0081 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0082 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0083 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0084 };
0085
0086 - |
0087 #include <dt-bindings/interrupt-controller/arm-gic.h>
0088 #include <dt-bindings/interrupt-controller/irq.h>
0089
0090 timer@2080000 {
0091 compatible = "nvidia,tegra234-timer";
0092 reg = <0x02080000 0x00121000>;
0093 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0094 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0095 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0096 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0097 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0098 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0099 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0100 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0101 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0102 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0103 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0104 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0105 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0106 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0107 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0108 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0109 };
