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OSCL-LXR

 
 

    


0001 J-Core Programmable Interval Timer and Clocksource
0002 
0003 Required properties:
0004 
0005 - compatible: Must be "jcore,pit".
0006 
0007 - reg: Memory region(s) for timer/clocksource registers. For SMP,
0008   there should be one region per cpu, indexed by the sequential,
0009   zero-based hardware cpu number.
0010 
0011 - interrupts: An interrupt to assign for the timer. The actual pit
0012   core is integrated with the aic and allows the timer interrupt
0013   assignment to be programmed by software, but this property is
0014   required in order to reserve an interrupt number that doesn't
0015   conflict with other devices.
0016 
0017 
0018 Example:
0019 
0020 timer@200 {
0021         compatible = "jcore,pit";
0022         reg = < 0x200 0x30 0x500 0x30 >;
0023         interrupts = < 0x48 >;
0024 };