0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM sp804 Dual Timers
0008
0009 maintainers:
0010 - Haojian Zhuang <haojian.zhuang@linaro.org>
0011
0012 description: |+
0013 The Arm SP804 IP implements two independent timers, configurable for
0014 16 or 32 bit operation and capable of running in one-shot, periodic, or
0015 free-running mode. The input clock is shared, but can be gated and prescaled
0016 independently for each timer.
0017
0018 There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
0019 SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804".
0020
0021 # Need a custom select here or 'arm,primecell' will match on lots of nodes
0022 select:
0023 properties:
0024 compatible:
0025 contains:
0026 enum:
0027 - arm,sp804
0028 - hisilicon,sp804
0029 required:
0030 - compatible
0031
0032 properties:
0033 compatible:
0034 items:
0035 - enum:
0036 - arm,sp804
0037 - hisilicon,sp804
0038 - const: arm,primecell
0039
0040 interrupts:
0041 description: |
0042 If two interrupts are listed, those are the interrupts for timer
0043 1 and 2, respectively. If there is only a single interrupt, it is
0044 either a combined interrupt or the sole interrupt of one timer, as
0045 specified by the "arm,sp804-has-irq" property.
0046 minItems: 1
0047 maxItems: 2
0048
0049 reg:
0050 description: The physical base address of the SP804 IP.
0051 maxItems: 1
0052
0053 clocks:
0054 description: |
0055 Clocks driving the dual timer hardware. This list should
0056 be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
0057 clock, apb_pclk. A single clock can also be specified if the same
0058 clock is used for all clock inputs.
0059 oneOf:
0060 - items:
0061 - description: clock for timer 1
0062 - description: clock for timer 2
0063 - description: bus clock
0064 - items:
0065 - description: unified clock for both timers and the bus
0066
0067 clock-names: true
0068 # The original binding did not specify any clock names, and there is no
0069 # consistent naming used in the existing DTs. The primecell binding
0070 # requires the "apb_pclk" name, so we need this property.
0071 # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs.
0072
0073 arm,sp804-has-irq:
0074 description: If only one interrupt line is connected to the interrupt
0075 controller, this property specifies which timer is connected to this
0076 line.
0077 $ref: /schemas/types.yaml#/definitions/uint32
0078 minimum: 1
0079 maximum: 2
0080
0081 required:
0082 - compatible
0083 - interrupts
0084 - reg
0085 - clocks
0086
0087 additionalProperties: false
0088
0089 examples:
0090 - |
0091 timer0: timer@fc800000 {
0092 compatible = "arm,sp804", "arm,primecell";
0093 reg = <0xfc800000 0x1000>;
0094 interrupts = <0 0 4>, <0 1 4>;
0095 clocks = <&timclk1>, <&timclk2>, <&pclk>;
0096 clock-names = "timer1", "timer2", "apb_pclk";
0097 };
