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0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: ARM architected timer
0008 
0009 maintainers:
0010   - Marc Zyngier <marc.zyngier@arm.com>
0011   - Mark Rutland <mark.rutland@arm.com>
0012 description: |+
0013   ARM cores may have a per-core architected timer, which provides per-cpu timers,
0014   or a memory mapped architected timer, which provides up to 8 frames with a
0015   physical and optional virtual timer per frame.
0016 
0017   The per-core architected timer is attached to a GIC to deliver its
0018   per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
0019   to deliver its interrupts via SPIs.
0020 
0021 properties:
0022   compatible:
0023     oneOf:
0024       - items:
0025           - enum:
0026               - arm,cortex-a15-timer
0027           - enum:
0028               - arm,armv7-timer
0029       - items:
0030           - enum:
0031               - arm,armv7-timer
0032       - items:
0033           - enum:
0034               - arm,armv8-timer
0035 
0036   interrupts:
0037     minItems: 1
0038     items:
0039       - description: secure timer irq
0040       - description: non-secure timer irq
0041       - description: virtual timer irq
0042       - description: hypervisor timer irq
0043       - description: hypervisor virtual timer irq
0044 
0045   interrupt-names:
0046     oneOf:
0047       - minItems: 2
0048         items:
0049           - const: phys
0050           - const: virt
0051           - const: hyp-phys
0052           - const: hyp-virt
0053       - minItems: 3
0054         items:
0055           - const: sec-phys
0056           - const: phys
0057           - const: virt
0058           - const: hyp-phys
0059           - const: hyp-virt
0060 
0061   clock-frequency:
0062     description: The frequency of the main counter, in Hz. Should be present
0063       only where necessary to work around broken firmware which does not configure
0064       CNTFRQ on all CPUs to a uniform correct value. Use of this property is
0065       strongly discouraged; fix your firmware unless absolutely impossible.
0066 
0067   always-on:
0068     type: boolean
0069     description: If present, the timer is powered through an always-on power
0070       domain, therefore it never loses context.
0071 
0072   allwinner,erratum-unknown1:
0073     type: boolean
0074     description: Indicates the presence of an erratum found in Allwinner SoCs,
0075       where reading certain values from the counter is unreliable. This also
0076       affects writes to the tval register, due to the implicit counter read.
0077 
0078   fsl,erratum-a008585:
0079     type: boolean
0080     description: Indicates the presence of QorIQ erratum A-008585, which says
0081       that reading the counter is unreliable unless the same value is returned
0082       by back-to-back reads. This also affects writes to the tval register, due
0083       to the implicit counter read.
0084 
0085   hisilicon,erratum-161010101:
0086     type: boolean
0087     description: Indicates the presence of Hisilicon erratum 161010101, which
0088       says that reading the counters is unreliable in some cases, and reads may
0089       return a value 32 beyond the correct value. This also affects writes to
0090       the tval registers, due to the implicit counter read.
0091 
0092   arm,cpu-registers-not-fw-configured:
0093     type: boolean
0094     description: Firmware does not initialize any of the generic timer CPU
0095       registers, which contain their architecturally-defined reset values. Only
0096       supported for 32-bit systems which follow the ARMv7 architected reset
0097       values.
0098 
0099   arm,no-tick-in-suspend:
0100     type: boolean
0101     description: The main counter does not tick when the system is in
0102       low-power system suspend on some SoCs. This behavior does not match the
0103       Architecture Reference Manual's specification that the system counter "must
0104       be implemented in an always-on power domain."
0105 
0106 required:
0107   - compatible
0108 
0109 additionalProperties: false
0110 
0111 oneOf:
0112   - required:
0113       - interrupts
0114   - required:
0115       - interrupts-extended
0116 
0117 examples:
0118   - |
0119     timer {
0120       compatible = "arm,cortex-a15-timer",
0121              "arm,armv7-timer";
0122       interrupts = <1 13 0xf08>,
0123              <1 14 0xf08>,
0124              <1 11 0xf08>,
0125              <1 10 0xf08>;
0126       clock-frequency = <100000000>;
0127     };
0128 
0129 ...