0001 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 # Copyright 2019 Linaro Ltd.
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: QCOM SoC Temperature Sensor (TSENS)
0009
0010 maintainers:
0011 - Amit Kucheria <amitk@kernel.org>
0012
0013 description: |
0014 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
0015 three distinct major versions of the IP that is supported by a single driver.
0016 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
0017 everything before v1 when there was no versioning information.
0018
0019 properties:
0020 compatible:
0021 oneOf:
0022 - description: msm8960 TSENS based
0023 items:
0024 - enum:
0025 - qcom,ipq8064-tsens
0026 - qcom,msm8960-tsens
0027
0028 - description: v0.1 of TSENS
0029 items:
0030 - enum:
0031 - qcom,mdm9607-tsens
0032 - qcom,msm8916-tsens
0033 - qcom,msm8939-tsens
0034 - qcom,msm8974-tsens
0035 - const: qcom,tsens-v0_1
0036
0037 - description: v1 of TSENS
0038 items:
0039 - enum:
0040 - qcom,msm8976-tsens
0041 - qcom,qcs404-tsens
0042 - const: qcom,tsens-v1
0043
0044 - description: v2 of TSENS
0045 items:
0046 - enum:
0047 - qcom,msm8953-tsens
0048 - qcom,msm8996-tsens
0049 - qcom,msm8998-tsens
0050 - qcom,sc7180-tsens
0051 - qcom,sc7280-tsens
0052 - qcom,sc8180x-tsens
0053 - qcom,sc8280xp-tsens
0054 - qcom,sdm630-tsens
0055 - qcom,sdm845-tsens
0056 - qcom,sm6350-tsens
0057 - qcom,sm8150-tsens
0058 - qcom,sm8250-tsens
0059 - qcom,sm8350-tsens
0060 - const: qcom,tsens-v2
0061
0062 reg:
0063 items:
0064 - description: TM registers
0065 - description: SROT registers
0066
0067 interrupts:
0068 minItems: 1
0069 items:
0070 - description: Combined interrupt if upper or lower threshold crossed
0071 - description: Interrupt if critical threshold crossed
0072
0073 interrupt-names:
0074 minItems: 1
0075 items:
0076 - const: uplow
0077 - const: critical
0078
0079 nvmem-cells:
0080 minItems: 1
0081 maxItems: 2
0082 description:
0083 Reference to an nvmem node for the calibration data
0084
0085 nvmem-cell-names:
0086 minItems: 1
0087 items:
0088 - const: calib
0089 - enum:
0090 - calib_backup
0091 - calib_sel
0092
0093 "#qcom,sensors":
0094 description:
0095 Number of sensors enabled on this platform
0096 $ref: /schemas/types.yaml#/definitions/uint32
0097 minimum: 1
0098 maximum: 16
0099
0100 "#thermal-sensor-cells":
0101 const: 1
0102 description:
0103 Number of cells required to uniquely identify the thermal sensors. Since
0104 we have multiple sensors this is set to 1
0105
0106 required:
0107 - compatible
0108 - interrupts
0109 - interrupt-names
0110 - "#thermal-sensor-cells"
0111 - "#qcom,sensors"
0112
0113 allOf:
0114 - if:
0115 properties:
0116 compatible:
0117 contains:
0118 enum:
0119 - qcom,ipq8064-tsens
0120 - qcom,mdm9607-tsens
0121 - qcom,msm8916-tsens
0122 - qcom,msm8960-tsens
0123 - qcom,msm8974-tsens
0124 - qcom,msm8976-tsens
0125 - qcom,qcs404-tsens
0126 - qcom,tsens-v0_1
0127 - qcom,tsens-v1
0128 then:
0129 properties:
0130 interrupts:
0131 maxItems: 1
0132 interrupt-names:
0133 maxItems: 1
0134
0135 else:
0136 properties:
0137 interrupts:
0138 minItems: 2
0139 interrupt-names:
0140 minItems: 2
0141
0142 - if:
0143 properties:
0144 compatible:
0145 contains:
0146 enum:
0147 - qcom,tsens-v0_1
0148 - qcom,tsens-v1
0149 - qcom,tsens-v2
0150
0151 then:
0152 required:
0153 - reg
0154
0155 additionalProperties: false
0156
0157 examples:
0158 - |
0159 #include <dt-bindings/interrupt-controller/arm-gic.h>
0160 // Example msm9860 based SoC (ipq8064):
0161 gcc: clock-controller {
0162
0163 /* ... */
0164
0165 tsens: thermal-sensor {
0166 compatible = "qcom,ipq8064-tsens";
0167
0168 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
0169 nvmem-cell-names = "calib", "calib_backup";
0170 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
0171 interrupt-names = "uplow";
0172
0173 #qcom,sensors = <11>;
0174 #thermal-sensor-cells = <1>;
0175 };
0176 };
0177
0178 - |
0179 #include <dt-bindings/interrupt-controller/arm-gic.h>
0180 // Example 1 (legacy: for pre v1 IP):
0181 tsens1: thermal-sensor@900000 {
0182 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
0183 reg = <0x4a9000 0x1000>, /* TM */
0184 <0x4a8000 0x1000>; /* SROT */
0185
0186 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
0187 nvmem-cell-names = "calib", "calib_sel";
0188
0189 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0190 interrupt-names = "uplow";
0191
0192 #qcom,sensors = <5>;
0193 #thermal-sensor-cells = <1>;
0194 };
0195
0196 - |
0197 #include <dt-bindings/interrupt-controller/arm-gic.h>
0198 // Example 2 (for any platform containing v1 of the TSENS IP):
0199 tsens2: thermal-sensor@4a9000 {
0200 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
0201 reg = <0x004a9000 0x1000>, /* TM */
0202 <0x004a8000 0x1000>; /* SROT */
0203
0204 nvmem-cells = <&tsens_caldata>;
0205 nvmem-cell-names = "calib";
0206
0207 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
0208 interrupt-names = "uplow";
0209
0210 #qcom,sensors = <10>;
0211 #thermal-sensor-cells = <1>;
0212 };
0213
0214 - |
0215 #include <dt-bindings/interrupt-controller/arm-gic.h>
0216 // Example 3 (for any platform containing v2 of the TSENS IP):
0217 tsens3: thermal-sensor@c263000 {
0218 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
0219 reg = <0xc263000 0x1ff>,
0220 <0xc222000 0x1ff>;
0221
0222 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
0223 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
0224 interrupt-names = "uplow", "critical";
0225
0226 #qcom,sensors = <13>;
0227 #thermal-sensor-cells = <1>;
0228 };
0229 ...
