0001 Tegra124 SOCTHERM thermal management system
0002
0003 The SOCTHERM IP block contains thermal sensors, support for polled
0004 or interrupt-based thermal monitoring, CPU and GPU throttling based
0005 on temperature trip points, and handling external overcurrent
0006 notifications. It is also used to manage emergency shutdown in an
0007 overheating situation.
0008
0009 Required properties :
0010 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
0011 For Tegra132, must contain "nvidia,tegra132-soctherm".
0012 For Tegra210, must contain "nvidia,tegra210-soctherm".
0013 - reg : Should contain at least 2 entries for each entry in reg-names:
0014 - SOCTHERM register set
0015 - Tegra CAR register set: Required for Tegra124 and Tegra210.
0016 - CCROC register set: Required for Tegra132.
0017 - reg-names : Should contain at least 2 entries:
0018 - soctherm-reg
0019 - car-reg
0020 - ccroc-reg
0021 - interrupts : Defines the interrupt used by SOCTHERM
0022 - clocks : Must contain an entry for each entry in clock-names.
0023 See ../clocks/clock-bindings.txt for details.
0024 - clock-names : Must include the following entries:
0025 - tsensor
0026 - soctherm
0027 - resets : Must contain an entry for each entry in reset-names.
0028 See ../reset/reset.txt for details.
0029 - reset-names : Must include the following entries:
0030 - soctherm
0031 - #thermal-sensor-cells : Should be 1. For a description of this property, see
0032 Documentation/devicetree/bindings/thermal/thermal-sensor.yaml.
0033 See <dt-bindings/thermal/tegra124-soctherm.h> for a list of valid values
0034 when referring to thermal sensors.
0035 - throttle-cfgs: A sub-node which is a container of configuration for each
0036 hardware throttle events. These events can be set as cooling devices.
0037 * throttle events: Sub-nodes must be named as "light" or "heavy".
0038 Properties:
0039 - nvidia,priority: Each throttles has its own throttle settings, so the
0040 SW need to set priorities for various throttle, the HW arbiter can select
0041 the final throttle settings.
0042 Bigger value indicates higher priority, In general, higher priority
0043 translates to lower target frequency. SW needs to ensure that critical
0044 thermal alarms are given higher priority, and ensure that there is
0045 no race if priority of two vectors is set to the same value.
0046 The range of this value is 1~100.
0047 - nvidia,cpu-throt-percent: This property is for Tegra124 and Tegra210.
0048 It is the throttling depth of pulse skippers, it's the percentage
0049 throttling.
0050 - nvidia,cpu-throt-level: This property is only for Tegra132, it is the
0051 level of pulse skippers, which used to throttle clock frequencies. It
0052 indicates cpu clock throttling depth, and the depth can be programmed.
0053 Must set as following values:
0054 TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED
0055 TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE
0056 - nvidia,gpu-throt-level: This property is for Tegra124 and Tegra210.
0057 It is the level of pulse skippers, which used to throttle clock
0058 frequencies. It indicates gpu clock throttling depth and can be
0059 programmed to any of the following values which represent a throttling
0060 percentage:
0061 TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%)
0062 TEGRA_SOCTHERM_THROT_LEVEL_LOW (50%),
0063 TEGRA_SOCTHERM_THROT_LEVEL_MED (75%),
0064 TEGRA_SOCTHERM_THROT_LEVEL_HIGH (85%).
0065 - #cooling-cells: Should be 1. This cooling device only support on/off state.
0066 For a description of this property see:
0067 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
0068
0069 Optional properties: The following properties are T210 specific and
0070 valid only for OCx throttle events.
0071 - nvidia,count-threshold: Specifies the number of OC events that are
0072 required for triggering an interrupt. Interrupts are not triggered if
0073 the property is missing. A value of 0 will interrupt on every OC alarm.
0074 - nvidia,polarity-active-low: Configures the polarity of the OC alaram
0075 signal. If present, this means assert low, otherwise assert high.
0076 - nvidia,alarm-filter: Number of clocks to filter event. When the filter
0077 expires (which means the OC event has not occurred for a long time),
0078 the counter is cleared and filter is rearmed. Default value is 0.
0079 - nvidia,throttle-period-us: Specifies the number of uSec for which
0080 throttling is engaged after the OC event is deasserted. Default value
0081 is 0.
0082
0083 Optional properties:
0084 - nvidia,thermtrips : When present, this property specifies the temperature at
0085 which the soctherm hardware will assert the thermal trigger signal to the
0086 Power Management IC, which can be configured to reset or shutdown the device.
0087 It is an array of pairs where each pair represents a tsensor id followed by a
0088 temperature in milli Celcius. In the absence of this property the critical
0089 trip point will be used for thermtrip temperature.
0090
0091 Note:
0092 - the "critical" type trip points will be used to set the temperature at which
0093 the SOC_THERM hardware will assert a thermal trigger if the "nvidia,thermtrips"
0094 property is missing. When the thermtrips property is present, the breach of a
0095 critical trip point is reported back to the thermal framework to implement
0096 software shutdown.
0097
0098 - the "hot" type trip points will be set to SOC_THERM hardware as the throttle
0099 temperature. Once the temperature of this thermal zone is higher
0100 than it, it will trigger the HW throttle event.
0101
0102 Example :
0103
0104 soctherm@700e2000 {
0105 compatible = "nvidia,tegra124-soctherm";
0106 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
0107 0x0 0x60006000 0x0 0x400 /* CAR reg_base */
0108 reg-names = "soctherm-reg", "car-reg";
0109 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0110 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
0111 <&tegra_car TEGRA124_CLK_SOC_THERM>;
0112 clock-names = "tsensor", "soctherm";
0113 resets = <&tegra_car 78>;
0114 reset-names = "soctherm";
0115
0116 #thermal-sensor-cells = <1>;
0117
0118 nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500
0119 TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
0120
0121 throttle-cfgs {
0122 /*
0123 * When the "heavy" cooling device triggered,
0124 * the HW will skip cpu clock's pulse in 85% depth,
0125 * skip gpu clock's pulse in 85% level
0126 */
0127 throttle_heavy: heavy {
0128 nvidia,priority = <100>;
0129 nvidia,cpu-throt-percent = <85>;
0130 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
0131
0132 #cooling-cells = <1>;
0133 };
0134
0135 /*
0136 * When the "light" cooling device triggered,
0137 * the HW will skip cpu clock's pulse in 50% depth,
0138 * skip gpu clock's pulse in 50% level
0139 */
0140 throttle_light: light {
0141 nvidia,priority = <80>;
0142 nvidia,cpu-throt-percent = <50>;
0143 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>;
0144
0145 #cooling-cells = <1>;
0146 };
0147
0148 /*
0149 * If these two devices are triggered in same time, the HW throttle
0150 * arbiter will select the highest priority as the final throttle
0151 * settings to skip cpu pulse.
0152 */
0153
0154 throttle_oc1: oc1 {
0155 nvidia,priority = <50>;
0156 nvidia,polarity-active-low;
0157 nvidia,count-threshold = <100>;
0158 nvidia,alarm-filter = <5100000>;
0159 nvidia,throttle-period-us = <0>;
0160 nvidia,cpu-throt-percent = <75>;
0161 nvidia,gpu-throt-level =
0162 <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
0163 };
0164 };
0165 };
0166
0167 Example: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" :
0168
0169 soctherm@700e2000 {
0170 compatible = "nvidia,tegra132-soctherm";
0171 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
0172 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
0173 reg-names = "soctherm-reg", "ccroc-reg";
0174
0175 throttle-cfgs {
0176 /*
0177 * When the "heavy" cooling device triggered,
0178 * the HW will skip cpu clock's pulse in HIGH level
0179 */
0180 throttle_heavy: heavy {
0181 nvidia,priority = <100>;
0182 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
0183
0184 #cooling-cells = <1>;
0185 };
0186
0187 /*
0188 * When the "light" cooling device triggered,
0189 * the HW will skip cpu clock's pulse in MED level
0190 */
0191 throttle_light: light {
0192 nvidia,priority = <80>;
0193 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
0194
0195 #cooling-cells = <1>;
0196 };
0197
0198 /*
0199 * If these two devices are triggered in same time, the HW throttle
0200 * arbiter will select the highest priority as the final throttle
0201 * settings to skip cpu pulse.
0202 */
0203
0204 };
0205 };
0206
0207 Example: referring to thermal sensors :
0208
0209 thermal-zones {
0210 cpu {
0211 polling-delay-passive = <1000>;
0212 polling-delay = <1000>;
0213
0214 thermal-sensors =
0215 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
0216
0217 trips {
0218 cpu_shutdown_trip: shutdown-trip {
0219 temperature = <102500>;
0220 hysteresis = <1000>;
0221 type = "critical";
0222 };
0223
0224 cpu_throttle_trip: throttle-trip {
0225 temperature = <100000>;
0226 hysteresis = <1000>;
0227 type = "hot";
0228 };
0229 };
0230
0231 cooling-maps {
0232 map0 {
0233 trip = <&cpu_throttle_trip>;
0234 cooling-device = <&throttle_heavy 1 1>;
0235 };
0236 };
0237 };
0238 };
