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OSCL-LXR

 
 

    


0001 * Mediatek Thermal
0002 
0003 This describes the device tree binding for the Mediatek thermal controller
0004 which measures the on-SoC temperatures. This device does not have its own ADC,
0005 instead it directly controls the AUXADC via AHB bus accesses. For this reason
0006 this device needs phandles to the AUXADC. Also it controls a mux in the
0007 apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
0008 is also needed.
0009 
0010 Required properties:
0011 - compatible:
0012   - "mediatek,mt8173-thermal" : For MT8173 family of SoCs
0013   - "mediatek,mt2701-thermal" : For MT2701 family of SoCs
0014   - "mediatek,mt2712-thermal" : For MT2712 family of SoCs
0015   - "mediatek,mt7622-thermal" : For MT7622 SoC
0016   - "mediatek,mt8183-thermal" : For MT8183 family of SoCs
0017   - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs
0018 - reg: Address range of the thermal controller
0019 - interrupts: IRQ for the thermal controller
0020 - clocks, clock-names: Clocks needed for the thermal controller. required
0021                        clocks are:
0022                        "therm":  Main clock needed for register access
0023                        "auxadc": The AUXADC clock
0024 - mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses
0025 - mediatek,apmixedsys: A phandle to the APMIXEDSYS controller.
0026 - #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
0027 
0028 Optional properties:
0029 - resets: Reference to the reset controller controlling the thermal controller.
0030 - nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
0031                unspecified default values shall be used.
0032 - nvmem-cell-names: Should be "calibration-data"
0033 
0034 Example:
0035 
0036         thermal: thermal@1100b000 {
0037                 #thermal-sensor-cells = <1>;
0038                 compatible = "mediatek,mt8173-thermal";
0039                 reg = <0 0x1100b000 0 0x1000>;
0040                 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
0041                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
0042                 clock-names = "therm", "auxadc";
0043                 resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
0044                 reset-names = "therm";
0045                 mediatek,auxadc = <&auxadc>;
0046                 mediatek,apmixedsys = <&apmixedsys>;
0047                 nvmem-cells = <&thermal_calibration_data>;
0048                 nvmem-cell-names = "calibration-data";
0049         };