bindings/spi/xlnx%2Czynq-qspi.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Xilinx Zynq QSPI controller
0008
0009 description:
0010   The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
0011   memory devices.
0012
0013 allOf:
0014   - $ref: "spi-controller.yaml#"
0015
0016 maintainers:
0017   - Michal Simek <michal.simek@xilinx.com>
0018
0019 # Everything else is described in the common file
0020 properties:
0021   compatible:
0022     const: xlnx,zynq-qspi-1.0
0023
0024   reg:
0025     maxItems: 1
0026
0027   interrupts:
0028     maxItems: 1
0029
0030   clocks:
0031     items:
0032       - description: reference clock
0033       - description: peripheral clock
0034
0035   clock-names:
0036     items:
0037       - const: ref_clk
0038       - const: pclk
0039
0040 required:
0041   - compatible
0042   - reg
0043   - interrupts
0044   - clocks
0045   - clock-names
0046
0047 unevaluatedProperties: false
0048
0049 examples:
0050   - |
0051     spi@e000d000 {
0052         compatible = "xlnx,zynq-qspi-1.0";
0053         reg = <0xe000d000 0x1000>;
0054         interrupt-parent = <&intc>;
0055         interrupts = <0 19 4>;
0056         clock-names = "ref_clk", "pclk";
0057         clocks = <&clkc 10>, <&clkc 43>;
0058         num-cs = <1>;
0059     };