0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings
0008
0009 maintainers:
0010 - Christophe Kerello <christophe.kerello@foss.st.com>
0011 - Patrice Chotard <patrice.chotard@foss.st.com>
0012
0013 allOf:
0014 - $ref: "spi-controller.yaml#"
0015
0016 properties:
0017 compatible:
0018 const: st,stm32f469-qspi
0019
0020 reg:
0021 items:
0022 - description: registers
0023 - description: memory mapping
0024
0025 reg-names:
0026 items:
0027 - const: qspi
0028 - const: qspi_mm
0029
0030 clocks:
0031 maxItems: 1
0032
0033 interrupts:
0034 maxItems: 1
0035
0036 resets:
0037 maxItems: 1
0038
0039 dmas:
0040 items:
0041 - description: tx DMA channel
0042 - description: rx DMA channel
0043
0044 dma-names:
0045 items:
0046 - const: tx
0047 - const: rx
0048
0049 required:
0050 - compatible
0051 - reg
0052 - reg-names
0053 - clocks
0054 - interrupts
0055
0056 unevaluatedProperties: false
0057
0058 examples:
0059 - |
0060 #include <dt-bindings/interrupt-controller/arm-gic.h>
0061 #include <dt-bindings/clock/stm32mp1-clks.h>
0062 #include <dt-bindings/reset/stm32mp1-resets.h>
0063 spi@58003000 {
0064 compatible = "st,stm32f469-qspi";
0065 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
0066 reg-names = "qspi", "qspi_mm";
0067 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0068 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
0069 <&mdma1 22 0x10 0x100008 0x0 0x0>;
0070 dma-names = "tx", "rx";
0071 clocks = <&rcc QSPI_K>;
0072 resets = <&rcc QSPI_R>;
0073
0074 #address-cells = <1>;
0075 #size-cells = <0>;
0076
0077 flash@0 {
0078 compatible = "jedec,spi-nor";
0079 reg = <0>;
0080 spi-rx-bus-width = <4>;
0081 spi-max-frequency = <108000000>;
0082 };
0083 };
0084
0085 ...
