0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: Spreadtrum ADI controller
0009
0010 maintainers:
0011 - Orson Zhai <orsonzhai@gmail.com>
0012 - Baolin Wang <baolin.wang7@gmail.com>
0013 - Chunyan Zhang <zhang.lyra@gmail.com>
0014
0015 description: |
0016 ADI is the abbreviation of Anolog-Digital interface, which is used to access
0017 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
0018 framework for its hardware implementation is alike to SPI bus and its timing
0019 is compatile to SPI timing.
0020
0021 ADI controller has 50 channels including 2 software read/write channels and
0022 48 hardware channels to access analog chip. For 2 software read/write channels,
0023 users should set ADI registers to access analog chip. For hardware channels,
0024 we can configure them to allow other hardware components to use it independently,
0025 which means we can just link one analog chip address to one hardware channel,
0026 then users can access the mapped analog chip address by this hardware channel
0027 triggered by hardware components instead of ADI software channels.
0028
0029 Thus we introduce one property named "sprd,hw-channels" to configure hardware
0030 channels, the first value specifies the hardware channel id which is used to
0031 transfer data triggered by hardware automatically, and the second value specifies
0032 the analog chip address where user want to access by hardware components.
0033
0034 Since we have multi-subsystems will use unique ADI to access analog chip, when
0035 one system is reading/writing data by ADI software channels, that should be under
0036 one hardware spinlock protection to prevent other systems from reading/writing
0037 data by ADI software channels at the same time, or two parallel routine of setting
0038 ADI registers will make ADI controller registers chaos to lead incorrect results.
0039 Then we need one hardware spinlock to synchronize between the multiple subsystems.
0040
0041 The new version ADI controller supplies multiple master channels for different
0042 subsystem accessing, that means no need to add hardware spinlock to synchronize,
0043 thus change the hardware spinlock support to be optional to keep backward
0044 compatibility.
0045
0046 allOf:
0047 - $ref: /schemas/spi/spi-controller.yaml#
0048
0049 properties:
0050 compatible:
0051 enum:
0052 - sprd,sc9860-adi
0053 - sprd,sc9863-adi
0054 - sprd,ums512-adi
0055
0056 reg:
0057 maxItems: 1
0058
0059 hwlocks:
0060 maxItems: 1
0061
0062 hwlock-names:
0063 const: adi
0064
0065 sprd,hw-channels:
0066 $ref: /schemas/types.yaml#/definitions/uint32-matrix
0067 description: A list of hardware channels
0068 minItems: 1
0069 maxItems: 48
0070 items:
0071 items:
0072 - description: The hardware channel id which is used to transfer data
0073 triggered by hardware automatically, channel id 0-1 are for software
0074 use, 2-49 are hardware channels.
0075 minimum: 2
0076 maximum: 49
0077 - description: The analog chip address where user want to access by
0078 hardware components.
0079
0080 required:
0081 - compatible
0082 - reg
0083 - '#address-cells'
0084 - '#size-cells'
0085
0086 unevaluatedProperties: false
0087
0088 examples:
0089 - |
0090 aon {
0091 #address-cells = <2>;
0092 #size-cells = <2>;
0093
0094 adi_bus: spi@40030000 {
0095 compatible = "sprd,sc9860-adi";
0096 reg = <0 0x40030000 0 0x10000>;
0097 hwlocks = <&hwlock1 0>;
0098 hwlock-names = "adi";
0099 #address-cells = <1>;
0100 #size-cells = <0>;
0101 sprd,hw-channels = <30 0x8c20>;
0102 };
0103 };
0104 ...
