bindings/spi/spi-zynqmp-qspi.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
0008
0009 maintainers:
0010   - Michal Simek <michal.simek@xilinx.com>
0011
0012 allOf:
0013   - $ref: "spi-controller.yaml#"
0014
0015 properties:
0016   compatible:
0017     const: xlnx,zynqmp-qspi-1.0
0018
0019   reg:
0020     maxItems: 2
0021
0022   interrupts:
0023     maxItems: 1
0024
0025   clock-names:
0026     items:
0027       - const: ref_clk
0028       - const: pclk
0029
0030   clocks:
0031     maxItems: 2
0032
0033 required:
0034   - compatible
0035   - reg
0036   - interrupts
0037   - clock-names
0038   - clocks
0039
0040 unevaluatedProperties: false
0041
0042 examples:
0043   - |
0044     #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
0045     soc {
0046       #address-cells = <2>;
0047       #size-cells = <2>;
0048
0049       qspi: spi@ff0f0000 {
0050         compatible = "xlnx,zynqmp-qspi-1.0";
0051         clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
0052         clock-names = "ref_clk", "pclk";
0053         interrupts = <0 15 4>;
0054         interrupt-parent = <&gic>;
0055         reg = <0x0 0xff0f0000 0x0 0x1000>,
0056               <0x0 0xc0000000 0x0 0x8000000>;
0057       };
0058     };