0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: SiFive SPI controller
0008
0009 maintainers:
0010 - Pragnesh Patel <pragnesh.patel@sifive.com>
0011 - Paul Walmsley <paul.walmsley@sifive.com>
0012 - Palmer Dabbelt <palmer@sifive.com>
0013
0014 allOf:
0015 - $ref: "spi-controller.yaml#"
0016
0017 properties:
0018 compatible:
0019 items:
0020 - enum:
0021 - sifive,fu540-c000-spi
0022 - sifive,fu740-c000-spi
0023 - const: sifive,spi0
0024
0025 description:
0026 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
0027 Supported compatible strings are -
0028 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
0029 as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"
0030 for the SiFive SPI v0 IP block with no chip integration tweaks.
0031 Please refer to sifive-blocks-ip-versioning.txt for details
0032
0033 SPI RTL that corresponds to the IP block version numbers can be found here -
0034 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
0035
0036 reg:
0037 minItems: 1
0038 items:
0039 - description: SPI registers region
0040 - description: Memory mapped flash region
0041
0042 interrupts:
0043 maxItems: 1
0044
0045 clocks:
0046 maxItems: 1
0047
0048 description:
0049 Must reference the frequency given to the controller
0050
0051 sifive,fifo-depth:
0052 description:
0053 Depth of hardware queues; defaults to 8
0054 $ref: "/schemas/types.yaml#/definitions/uint32"
0055 enum: [8]
0056 default: 8
0057
0058 sifive,max-bits-per-word:
0059 description:
0060 Maximum bits per word; defaults to 8
0061 $ref: "/schemas/types.yaml#/definitions/uint32"
0062 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
0063 default: 8
0064
0065 required:
0066 - compatible
0067 - reg
0068 - interrupts
0069 - clocks
0070
0071 unevaluatedProperties: false
0072
0073 examples:
0074 - |
0075 spi: spi@10040000 {
0076 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
0077 reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
0078 interrupt-parent = <&plic>;
0079 interrupts = <51>;
0080 clocks = <&tlclk>;
0081 #address-cells = <1>;
0082 #size-cells = <0>;
0083 sifive,fifo-depth = <8>;
0084 sifive,max-bits-per-word = <8>;
0085 };
0086
0087 ...
