0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/spi-pl022.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM PL022 SPI controller
0008
0009 maintainers:
0010 - Linus Walleij <linus.walleij@linaro.org>
0011
0012 allOf:
0013 - $ref: "spi-controller.yaml#"
0014
0015 # We need a select here so we don't match all nodes with 'arm,primecell'
0016 select:
0017 properties:
0018 compatible:
0019 contains:
0020 const: arm,pl022
0021 required:
0022 - compatible
0023
0024 properties:
0025 compatible:
0026 items:
0027 - const: arm,pl022
0028 - const: arm,primecell
0029
0030 reg:
0031 maxItems: 1
0032
0033 interrupts:
0034 maxItems: 1
0035
0036 clocks:
0037 maxItems: 2
0038
0039 clock-names:
0040 items:
0041 - const: sspclk
0042 - const: apb_pclk
0043
0044 pl022,autosuspend-delay:
0045 description: delay in ms following transfer completion before the
0046 runtime power management system suspends the device. A setting of 0
0047 indicates no delay and the device will be suspended immediately.
0048 $ref: "/schemas/types.yaml#/definitions/uint32"
0049
0050 pl022,rt:
0051 description: indicates the controller should run the message pump with realtime
0052 priority to minimise the transfer latency on the bus (boolean)
0053 type: boolean
0054
0055 dmas:
0056 description:
0057 Two or more DMA channel specifiers following the convention outlined
0058 in bindings/dma/dma.txt
0059 minItems: 2
0060 maxItems: 32
0061
0062 dma-names:
0063 description:
0064 There must be at least one channel named "tx" for transmit and named "rx"
0065 for receive.
0066 minItems: 2
0067 maxItems: 32
0068 additionalItems: true
0069 items:
0070 - const: rx
0071 - const: tx
0072
0073 resets:
0074 maxItems: 1
0075
0076 patternProperties:
0077 "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
0078 type: object
0079 # SPI slave nodes must be children of the SPI master node and can
0080 # contain the following properties.
0081 properties:
0082 pl022,interface:
0083 description: SPI interface type
0084 $ref: "/schemas/types.yaml#/definitions/uint32"
0085 enum:
0086 - 0 # SPI
0087 - 1 # Texas Instruments Synchronous Serial Frame Format
0088 - 2 # Microwire (Half Duplex)
0089
0090 pl022,com-mode:
0091 description: Specifies the transfer mode
0092 $ref: "/schemas/types.yaml#/definitions/uint32"
0093 enum:
0094 - 0 # interrupt mode
0095 - 1 # polling mode
0096 - 2 # DMA mode
0097 default: 1
0098
0099 pl022,rx-level-trig:
0100 description: Rx FIFO watermark level
0101 $ref: "/schemas/types.yaml#/definitions/uint32"
0102 minimum: 0
0103 maximum: 4
0104
0105 pl022,tx-level-trig:
0106 description: Tx FIFO watermark level
0107 $ref: "/schemas/types.yaml#/definitions/uint32"
0108 minimum: 0
0109 maximum: 4
0110
0111 pl022,ctrl-len:
0112 description: Microwire interface - Control length
0113 $ref: "/schemas/types.yaml#/definitions/uint32"
0114 minimum: 0x03
0115 maximum: 0x1f
0116
0117 pl022,wait-state:
0118 description: Microwire interface - Wait state
0119 $ref: "/schemas/types.yaml#/definitions/uint32"
0120 enum: [0, 1]
0121
0122 pl022,duplex:
0123 description: Microwire interface - Full/Half duplex
0124 $ref: "/schemas/types.yaml#/definitions/uint32"
0125 enum: [0, 1]
0126
0127 required:
0128 - compatible
0129 - reg
0130 - interrupts
0131
0132 unevaluatedProperties: false
0133
0134 examples:
0135 - |
0136 spi@e0100000 {
0137 compatible = "arm,pl022", "arm,primecell";
0138 reg = <0xe0100000 0x1000>;
0139 #address-cells = <1>;
0140 #size-cells = <0>;
0141 interrupts = <0 31 0x4>;
0142 dmas = <&dma_controller 23 1>,
0143 <&dma_controller 24 0>;
0144 dma-names = "rx", "tx";
0145
0146 flash@1 {
0147 compatible = "st,m25p80";
0148 reg = <1>;
0149 spi-max-frequency = <12000000>;
0150 spi-cpol;
0151 spi-cpha;
0152 pl022,interface = <0>;
0153 pl022,com-mode = <0x2>;
0154 pl022,rx-level-trig = <0>;
0155 pl022,tx-level-trig = <0>;
0156 pl022,ctrl-len = <0x11>;
0157 pl022,wait-state = <0>;
0158 pl022,duplex = <0>;
0159 };
0160 };
0161 ...
