0001 Marvell Orion SPI device
0002
0003 Required properties:
0004 - compatible : should be on of the following:
0005 - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
0006 - "marvell,armada-370-spi", for the Armada 370 SoCs
0007 - "marvell,armada-375-spi", for the Armada 375 SoCs
0008 - "marvell,armada-380-spi", for the Armada 38x SoCs
0009 - "marvell,armada-390-spi", for the Armada 39x SoCs
0010 - "marvell,armada-xp-spi", for the Armada XP SoCs
0011 - reg : offset and length of the register set for the device.
0012 This property can optionally have additional entries to configure
0013 the SPI direct access mode that some of the Marvell SoCs support
0014 additionally to the normal indirect access (PIO) mode. The values
0015 for the MBus "target" and "attribute" are defined in the Marvell
0016 SoC "Functional Specifications" Manual in the chapter "Marvell
0017 Core Processor Address Decoding".
0018 The eight register sets following the control registers refer to
0019 chip-select lines 0 through 7 respectively.
0020 - cell-index : Which of multiple SPI controllers is this.
0021 - clocks : pointers to the reference clocks for this device, the first
0022 one is the one used for the clock on the spi bus, the
0023 second one is optional and is the clock used for the
0024 functional part of the controller
0025
0026 Optional properties:
0027 - interrupts : Is currently not used.
0028 - clock-names : names of used clocks, mandatory if the second clock is
0029 used, the name must be "core", and "axi" (the latter
0030 is only for Armada 7K/8K).
0031
0032
0033 Example:
0034 spi@10600 {
0035 compatible = "marvell,orion-spi";
0036 #address-cells = <1>;
0037 #size-cells = <0>;
0038 cell-index = <0>;
0039 reg = <0x10600 0x28>;
0040 interrupts = <23>;
0041 };
0042
0043 Example with SPI direct mode support (optionally):
0044 spi0: spi@10600 {
0045 compatible = "marvell,orion-spi";
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048 cell-index = <0>;
0049 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
0050 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
0051 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
0052 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
0053 <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
0054 <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
0055 <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
0056 <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
0057 <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
0058 interrupts = <23>;
0059 };
0060
0061 To enable the direct mode, the board specific 'ranges' property in the
0062 'soc' node needs to add the entries for the desired SPI controllers
0063 and its chip-selects that are used in the direct mode instead of PIO
0064 mode. Here an example for this (SPI controller 0, device 1 and SPI
0065 controller 1, device 2 are used in direct mode. All other SPI device
0066 are used in the default indirect (PIO) mode):
0067 soc {
0068 /*
0069 * Enable the SPI direct access by configuring an entry
0070 * here in the board-specific ranges property
0071 */
0072 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>, /* internal regs */
0073 <MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>, /* BootROM */
0074 <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>, /* SPI0-DEV1 */
0075 <MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>; /* SPI1-DEV2 */
0076
0077 For further information on the MBus bindings, please see the MBus
0078 DT documentation:
0079 Documentation/devicetree/bindings/bus/mvebu-mbus.txt
