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OSCL-LXR

 
 

    


0001 Cavium, Inc. OCTEON SOC SPI master controller.
0002 
0003 Required properties:
0004 - compatible : "cavium,octeon-3010-spi"
0005 - reg : The register base for the controller.
0006 - interrupts : One interrupt, used by the controller.
0007 - #address-cells : <1>, as required by generic SPI binding.
0008 - #size-cells : <0>, also as required by generic SPI binding.
0009 
0010 Child nodes as per the generic SPI binding.
0011 
0012 Example:
0013 
0014         spi@1070000001000 {
0015                 compatible = "cavium,octeon-3010-spi";
0016                 reg = <0x10700 0x00001000 0x0 0x100>;
0017                 interrupts = <0 58>;
0018                 #address-cells = <1>;
0019                 #size-cells = <0>;
0020 
0021                 eeprom@0 {
0022                         compatible = "st,m95256", "atmel,at25";
0023                         reg = <0>;
0024                         spi-max-frequency = <5000000>;
0025                         spi-cpha;
0026                         spi-cpol;
0027 
0028                         pagesize = <64>;
0029                         size = <32768>;
0030                         address-width = <16>;
0031                 };
0032         };
0033