0001 Lantiq Synchronous Serial Controller (SSC) SPI master driver
0002
0003 Required properties:
0004 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
0005 "intel,lgm-spi"
0006 - #address-cells: see spi-bus.txt
0007 - #size-cells: see spi-bus.txt
0008 - reg: address and length of the spi master registers
0009 - interrupts:
0010 For compatible "intel,lgm-ssc" - the common interrupt number for
0011 all of tx rx & err interrupts.
0012 or
0013 For rest of the compatibles, should contain the "spi_rx", "spi_tx" and
0014 "spi_err" interrupt.
0015
0016
0017 Optional properties:
0018 - clocks: spi clock phandle
0019 - num-cs: see spi-bus.txt, set to 8 if unset
0020 - base-cs: the number of the first chip select, set to 1 if unset.
0021
0022 Example:
0023
0024
0025 spi: spi@e100800 {
0026 compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
0027 reg = <0xE100800 0x100>;
0028 interrupt-parent = <&icu0>;
0029 interrupts = <22 23 24>;
0030 interrupt-names = "spi_rx", "spi_tx", "spi_err";
0031 #address-cells = <1>;
0032 #size-cells = <1>;
0033 num-cs = <6>;
0034 base-cs = <1>;
0035 };
0036
0037 ssc0: spi@e0800000 {
0038 compatible = "intel,lgm-spi";
0039 reg = <0xe0800000 0x400>;
0040 interrupt-parent = <&ioapic1>;
0041 interrupts = <35 1>;
0042 #address-cells = <1>;
0043 #size-cells = <0>;
0044 clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>;
0045 clock-names = "freq", "gate";
0046 };
