0001 Davinci SPI controller device bindings
0002
0003 Links on DM:
0004 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
0005 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
0006 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
0007
0008 Required properties:
0009 - #address-cells: number of cells required to define a chip select
0010 address on the SPI bus. Should be set to 1.
0011 - #size-cells: should be zero.
0012 - compatible:
0013 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
0014 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
0015 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
0016 family
0017 - reg: Offset and length of SPI controller register space
0018 - num-cs: Number of chip selects. This includes internal as well as
0019 GPIO chip selects.
0020 - ti,davinci-spi-intr-line: interrupt line used to connect the SPI
0021 IP to the interrupt controller within the SoC. Possible values
0022 are 0 and 1. Manual says one of the two possible interrupt
0023 lines can be tied to the interrupt controller. Set this
0024 based on a specific SoC configuration.
0025 - interrupts: interrupt number mapped to CPU.
0026 - clocks: spi clk phandle
0027 For 66AK2G this property should be set per binding,
0028 Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
0029
0030 SoC-specific Required Properties:
0031
0032 The following are mandatory properties for Keystone 2 66AK2G SoCs only:
0033
0034 - power-domains: Should contain a phandle to a PM domain provider node
0035 and an args specifier containing the SPI device id
0036 value. This property is as per the binding,
0037
0038 Optional:
0039 - cs-gpios: gpio chip selects
0040 For example to have 3 internal CS and 2 GPIO CS, user could define
0041 cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
0042 where first three are internal CS and last two are GPIO CS.
0043
0044 Optional properties for slave devices:
0045 SPI slave nodes can contain the following properties.
0046 Not all SPI Peripherals from Texas Instruments support this.
0047 Please check SPI peripheral documentation for a device before using these.
0048
0049 - ti,spi-wdelay : delay between transmission of words
0050 (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module
0051 clock periods.
0052
0053 delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period
0054
0055 Below is timing diagram which shows functional meaning of
0056 "ti,spi-wdelay" parameter.
0057
0058 +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
0059 SPI_CLK | | | | | | | | | | | | | | | |
0060 +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +-
0061
0062 SPI_SOMI/SIMO+-----------------+ +-----------
0063 +----------+ word1 +---------------------------+word2
0064 +-----------------+ +-----------
0065 WDELAY
0066 <-------------------------->
0067
0068 Example of a NOR flash slave device (n25q032) connected to DaVinci
0069 SPI controller device over the SPI bus.
0070
0071 spi0:spi@20bf0000 {
0072 #address-cells = <1>;
0073 #size-cells = <0>;
0074 compatible = "ti,dm6446-spi";
0075 reg = <0x20BF0000 0x1000>;
0076 num-cs = <4>;
0077 ti,davinci-spi-intr-line = <0>;
0078 interrupts = <338>;
0079 clocks = <&clkspi>;
0080
0081 flash: flash@0 {
0082 #address-cells = <1>;
0083 #size-cells = <1>;
0084 compatible = "st,m25p32";
0085 spi-max-frequency = <25000000>;
0086 reg = <0>;
0087 ti,spi-wdelay = <8>;
0088
0089 partition@0 {
0090 label = "u-boot-spl";
0091 reg = <0x0 0x80000>;
0092 read-only;
0093 };
0094
0095 partition@1 {
0096 label = "test";
0097 reg = <0x80000 0x380000>;
0098 };
0099 };
0100 };
