bindings/spi/renesas%2Csh-msiof.yaml

0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas MSIOF SPI controller
0008
0009 maintainers:
0010   - Geert Uytterhoeven <geert+renesas@glider.be>
0011
0012 allOf:
0013   - $ref: spi-controller.yaml#
0014
0015 properties:
0016   compatible:
0017     oneOf:
0018       - items:
0019           - const: renesas,msiof-sh73a0     # SH-Mobile AG5
0020           - const: renesas,sh-mobile-msiof  # generic SH-Mobile compatible
0021                                             # device
0022       - items:
0023           - enum:
0024               - renesas,msiof-r8a7742       # RZ/G1H
0025               - renesas,msiof-r8a7743       # RZ/G1M
0026               - renesas,msiof-r8a7744       # RZ/G1N
0027               - renesas,msiof-r8a7745       # RZ/G1E
0028               - renesas,msiof-r8a77470      # RZ/G1C
0029               - renesas,msiof-r8a7790       # R-Car H2
0030               - renesas,msiof-r8a7791       # R-Car M2-W
0031               - renesas,msiof-r8a7792       # R-Car V2H
0032               - renesas,msiof-r8a7793       # R-Car M2-N
0033               - renesas,msiof-r8a7794       # R-Car E2
0034           - const: renesas,rcar-gen2-msiof  # generic R-Car Gen2 and RZ/G1
0035                                             # compatible device
0036       - items:
0037           - enum:
0038               - renesas,msiof-r8a774a1      # RZ/G2M
0039               - renesas,msiof-r8a774b1      # RZ/G2N
0040               - renesas,msiof-r8a774c0      # RZ/G2E
0041               - renesas,msiof-r8a774e1      # RZ/G2H
0042               - renesas,msiof-r8a7795       # R-Car H3
0043               - renesas,msiof-r8a7796       # R-Car M3-W
0044               - renesas,msiof-r8a77961      # R-Car M3-W+
0045               - renesas,msiof-r8a77965      # R-Car M3-N
0046               - renesas,msiof-r8a77970      # R-Car V3M
0047               - renesas,msiof-r8a77980      # R-Car V3H
0048               - renesas,msiof-r8a77990      # R-Car E3
0049               - renesas,msiof-r8a77995      # R-Car D3
0050               - renesas,msiof-r8a779a0      # R-Car V3U
0051           - const: renesas,rcar-gen3-msiof  # generic R-Car Gen3 and RZ/G2
0052                                             # compatible device
0053       - items:
0054           - const: renesas,sh-msiof  # deprecated
0055
0056   reg:
0057     minItems: 1
0058     maxItems: 2
0059     oneOf:
0060       - items:
0061           - description: CPU and DMA engine registers
0062       - items:
0063           - description: CPU registers
0064           - description: DMA engine registers
0065
0066   interrupts:
0067     maxItems: 1
0068
0069   clocks:
0070     maxItems: 1
0071
0072   num-cs:
0073     description: |
0074       Total number of chip selects (default is 1).
0075       Up to 3 native chip selects are supported:
0076         0: MSIOF_SYNC
0077         1: MSIOF_SS1
0078         2: MSIOF_SS2
0079       Hardware limitations related to chip selects:
0080         - Native chip selects are always deasserted in between transfers
0081           that are part of the same message.  Use cs-gpios to work around
0082           this.
0083         - All slaves using native chip selects must use the same spi-cs-high
0084           configuration.  Use cs-gpios to work around this.
0085         - When using GPIO chip selects, at least one native chip select must
0086           be left unused, as it will be driven anyway.
0087     minimum: 1
0088     maximum: 3
0089     default: 1
0090
0091   dmas:
0092     minItems: 2
0093     maxItems: 4
0094
0095   dma-names:
0096     minItems: 2
0097     maxItems: 4
0098     items:
0099       enum: [ tx, rx ]
0100
0101   renesas,dtdl:
0102     description: delay sync signal (setup) in transmit mode.
0103     $ref: /schemas/types.yaml#/definitions/uint32
0104     enum:
0105       - 0        # no bit delay
0106       - 50       # 0.5-clock-cycle delay
0107       - 100      # 1-clock-cycle delay
0108       - 150      # 1.5-clock-cycle delay
0109       - 200      # 2-clock-cycle delay
0110
0111   renesas,syncdl:
0112     description: delay sync signal (hold) in transmit mode
0113     $ref: /schemas/types.yaml#/definitions/uint32
0114     enum:
0115       - 0        # no bit delay
0116       - 50       # 0.5-clock-cycle delay
0117       - 100      # 1-clock-cycle delay
0118       - 150      # 1.5-clock-cycle delay
0119       - 200      # 2-clock-cycle delay
0120       - 300      # 3-clock-cycle delay
0121
0122   renesas,tx-fifo-size:
0123     # deprecated for soctype-specific bindings
0124     description: |
0125       Override the default TX fifo size.  Unit is words.  Ignored if 0.
0126     $ref: /schemas/types.yaml#/definitions/uint32
0127     default: 64
0128
0129   renesas,rx-fifo-size:
0130     # deprecated for soctype-specific bindings
0131     description: |
0132       Override the default RX fifo size.  Unit is words.  Ignored if 0.
0133     $ref: /schemas/types.yaml#/definitions/uint32
0134     default: 64
0135
0136 required:
0137   - compatible
0138   - reg
0139   - interrupts
0140   - '#address-cells'
0141   - '#size-cells'
0142
0143 unevaluatedProperties: false
0144
0145 examples:
0146   - |
0147     #include <dt-bindings/clock/r8a7791-clock.h>
0148     #include <dt-bindings/interrupt-controller/irq.h>
0149
0150     msiof0: spi@e6e20000 {
0151         compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof";
0152         reg = <0xe6e20000 0x0064>;
0153         interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
0154         clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
0155         dmas = <&dmac0 0x51>, <&dmac0 0x52>;
0156         dma-names = "tx", "rx";
0157         #address-cells = <1>;
0158         #size-cells = <0>;
0159     };