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0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007 
0008 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
0009 
0010 maintainers:
0011   - Bjorn Andersson <bjorn.andersson@linaro.org>
0012 
0013 description: The QSPI controller allows SPI protocol communication in single,
0014   dual, or quad wire transmission modes for read/write access to slaves such
0015   as NOR flash.
0016 
0017 allOf:
0018   - $ref: /schemas/spi/spi-controller.yaml#
0019 
0020 properties:
0021   compatible:
0022     items:
0023       - enum:
0024           - qcom,sc7180-qspi
0025           - qcom,sc7280-qspi
0026           - qcom,sdm845-qspi
0027 
0028       - const: qcom,qspi-v1
0029 
0030   reg:
0031     maxItems: 1
0032 
0033   interrupts:
0034     maxItems: 1
0035 
0036   clock-names:
0037     items:
0038       - const: iface
0039       - const: core
0040 
0041   clocks:
0042     items:
0043       - description: AHB clock
0044       - description: QSPI core clock
0045 
0046   interconnects:
0047     minItems: 1
0048     maxItems: 2
0049 
0050   interconnect-names:
0051     minItems: 1
0052     items:
0053       - const: qspi-config
0054       - const: qspi-memory
0055 
0056 required:
0057   - compatible
0058   - reg
0059   - interrupts
0060   - clock-names
0061   - clocks
0062 
0063 unevaluatedProperties: false
0064 
0065 examples:
0066   - |
0067     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
0068     #include <dt-bindings/interrupt-controller/arm-gic.h>
0069 
0070     soc: soc {
0071         #address-cells = <2>;
0072         #size-cells = <2>;
0073 
0074         qspi: spi@88df000 {
0075             compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
0076             reg = <0 0x88df000 0 0x600>;
0077             #address-cells = <1>;
0078             #size-cells = <0>;
0079             interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0080             clock-names = "iface", "core";
0081             clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
0082                          <&gcc GCC_QSPI_CORE_CLK>;
0083 
0084             flash@0 {
0085                 compatible = "jedec,spi-nor";
0086                 reg = <0>;
0087                 spi-max-frequency = <25000000>;
0088                 spi-tx-bus-width = <2>;
0089                 spi-rx-bus-width = <2>;
0090             };
0091 
0092         };
0093     };
0094 ...