0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
0008
0009 maintainers:
0010 - Andy Gross <agross@kernel.org>
0011 - Bjorn Andersson <bjorn.andersson@linaro.org>
0012 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
0013
0014 description:
0015 The QUP v3 core is a GENI based AHB slave that provides a common data path
0016 (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
0017 mini-core.
0018
0019 SPI in master mode supports up to 50MHz, up to four chip selects,
0020 programmable data path from 4 bits to 32 bits and numerous protocol variants.
0021
0022 SPI Controller nodes must be child of GENI based Qualcomm Universal
0023 Peripharal. Please refer GENI based QUP wrapper controller node bindings
0024 described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.
0025
0026 allOf:
0027 - $ref: /schemas/spi/spi-controller.yaml#
0028
0029 properties:
0030 compatible:
0031 const: qcom,geni-spi
0032
0033 clocks:
0034 maxItems: 1
0035
0036 clock-names:
0037 const: se
0038
0039 dmas:
0040 maxItems: 2
0041
0042 dma-names:
0043 items:
0044 - const: tx
0045 - const: rx
0046
0047 interconnects:
0048 minItems: 2
0049 maxItems: 3
0050
0051 interconnect-names:
0052 minItems: 2
0053 items:
0054 - const: qup-core
0055 - const: qup-config
0056 - const: qup-memory
0057
0058 interrupts:
0059 maxItems: 1
0060
0061 operating-points-v2: true
0062
0063 power-domains:
0064 maxItems: 1
0065
0066 reg:
0067 maxItems: 1
0068
0069 required:
0070 - compatible
0071 - clocks
0072 - clock-names
0073 - interrupts
0074 - reg
0075
0076 unevaluatedProperties: false
0077
0078 examples:
0079 - |
0080 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
0081 #include <dt-bindings/interconnect/qcom,sc7180.h>
0082 #include <dt-bindings/interrupt-controller/arm-gic.h>
0083 #include <dt-bindings/power/qcom-rpmpd.h>
0084
0085 spi@880000 {
0086 compatible = "qcom,geni-spi";
0087 reg = <0x00880000 0x4000>;
0088 clock-names = "se";
0089 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
0090 pinctrl-names = "default";
0091 pinctrl-0 = <&qup_spi0_default>;
0092 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
0093 #address-cells = <1>;
0094 #size-cells = <0>;
0095 power-domains = <&rpmhpd SC7180_CX>;
0096 operating-points-v2 = <&qup_opp_table>;
0097 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
0098 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
0099 interconnect-names = "qup-core", "qup-config";
0100 };
0101
0102 - |
0103 #include <dt-bindings/dma/qcom-gpi.h>
0104
0105 spi@884000 {
0106 compatible = "qcom,geni-spi";
0107 reg = <0x00884000 0x4000>;
0108 clock-names = "se";
0109 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
0110 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
0111 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
0112 dma-names = "tx", "rx";
0113 pinctrl-names = "default";
0114 pinctrl-0 = <&qup_spi1_default>;
0115 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
0116 #address-cells = <1>;
0117 #size-cells = <0>;
0118 };
