0001 NVIDIA Tegra20 SFLASH controller.
0002
0003 Required properties:
0004 - compatible : should be "nvidia,tegra20-sflash".
0005 - reg: Should contain SFLASH registers location and length.
0006 - interrupts: Should contain SFLASH interrupts.
0007 - clocks : Must contain one entry, for the module clock.
0008 See ../clocks/clock-bindings.txt for details.
0009 - resets : Must contain an entry for each entry in reset-names.
0010 See ../reset/reset.txt for details.
0011 - reset-names : Must include the following entries:
0012 - spi
0013 - dmas : Must contain an entry for each entry in clock-names.
0014 See ../dma/dma.txt for details.
0015 - dma-names : Must include the following entries:
0016 - rx
0017 - tx
0018
0019 Recommended properties:
0020 - spi-max-frequency: Definition as per
0021 Documentation/devicetree/bindings/spi/spi-bus.txt
0022
0023 Example:
0024
0025 spi@7000c380 {
0026 compatible = "nvidia,tegra20-sflash";
0027 reg = <0x7000c380 0x80>;
0028 interrupts = <0 39 0x04>;
0029 spi-max-frequency = <25000000>;
0030 #address-cells = <1>;
0031 #size-cells = <0>;
0032 clocks = <&tegra_car 43>;
0033 resets = <&tegra_car 43>;
0034 reset-names = "spi";
0035 dmas = <&apbdma 11>, <&apbdma 11>;
0036 dma-names = "rx", "tx";
0037 };
