0001 Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver
0002
0003 Nuvoton NPCM7xx SOC support two PSPI channels.
0004
0005 Required properties:
0006 - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC
0007 - #address-cells : should be 1. see spi-bus.txt
0008 - #size-cells : should be 0. see spi-bus.txt
0009 - specifies physical base address and size of the register.
0010 - interrupts : contain PSPI interrupt.
0011 - clocks : phandle of PSPI reference clock.
0012 - clock-names: Should be "clk_apb5".
0013 - pinctrl-names : a pinctrl state named "default" must be defined.
0014 - pinctrl-0 : phandle referencing pin configuration of the device.
0015 - resets : phandle to the reset control for this device.
0016 - cs-gpios: Specifies the gpio pins to be used for chipselects.
0017 See: Documentation/devicetree/bindings/spi/spi-bus.txt
0018
0019 Optional properties:
0020 - clock-frequency : Input clock frequency to the PSPI block in Hz.
0021 Default is 25000000 Hz.
0022
0023 spi0: spi@f0200000 {
0024 compatible = "nuvoton,npcm750-pspi";
0025 reg = <0xf0200000 0x1000>;
0026 pinctrl-names = "default";
0027 pinctrl-0 = <&pspi1_pins>;
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0031 clocks = <&clk NPCM7XX_CLK_APB5>;
0032 clock-names = "clk_apb5";
0033 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>
0034 cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
0035 };
