0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: SPI-NAND flash controller for MediaTek ARM SoCs
0008
0009 maintainers:
0010 - Chuanhong Guo <gch981213@gmail.com>
0011
0012 description: |
0013 The Mediatek SPI-NAND flash controller is an extended version of
0014 the Mediatek NAND flash controller. It can perform standard SPI
0015 instructions with one continuous write and one read for up-to 0xa0
0016 bytes. It also supports typical SPI-NAND page cache operations
0017 in single, dual or quad IO mode with pipelined ECC encoding/decoding
0018 using the accompanying ECC engine. There should be only one spi
0019 slave device following generic spi bindings.
0020
0021 allOf:
0022 - $ref: /schemas/spi/spi-controller.yaml#
0023
0024 properties:
0025 compatible:
0026 enum:
0027 - mediatek,mt7622-snand
0028 - mediatek,mt7629-snand
0029
0030 reg:
0031 items:
0032 - description: core registers
0033
0034 interrupts:
0035 items:
0036 - description: NFI interrupt
0037
0038 clocks:
0039 items:
0040 - description: clock used for the controller
0041 - description: clock used for the SPI bus
0042
0043 clock-names:
0044 items:
0045 - const: nfi_clk
0046 - const: pad_clk
0047
0048 nand-ecc-engine:
0049 description: device-tree node of the accompanying ECC engine.
0050 $ref: /schemas/types.yaml#/definitions/phandle
0051
0052 required:
0053 - compatible
0054 - reg
0055 - interrupts
0056 - clocks
0057 - clock-names
0058 - nand-ecc-engine
0059
0060 unevaluatedProperties: false
0061
0062 examples:
0063 - |
0064 #include <dt-bindings/interrupt-controller/irq.h>
0065 #include <dt-bindings/interrupt-controller/arm-gic.h>
0066 #include <dt-bindings/clock/mt7622-clk.h>
0067 soc {
0068 #address-cells = <2>;
0069 #size-cells = <2>;
0070 snfi: spi@1100d000 {
0071 compatible = "mediatek,mt7622-snand";
0072 reg = <0 0x1100d000 0 0x1000>;
0073 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
0074 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
0075 clock-names = "nfi_clk", "pad_clk";
0076 nand-ecc-engine = <&bch>;
0077 #address-cells = <1>;
0078 #size-cells = <0>;
0079
0080 flash@0 {
0081 compatible = "spi-nand";
0082 reg = <0>;
0083 spi-tx-bus-width = <4>;
0084 spi-rx-bus-width = <4>;
0085 nand-ecc-engine = <&snfi>;
0086 };
0087 };
0088 };
