bindings/spi/fsl%2Cspi-fsl-qspi.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Freescale Quad Serial Peripheral Interface (QuadSPI)
0008
0009 maintainers:
0010   - Han Xu <han.xu@nxp.com>
0011
0012 allOf:
0013   - $ref: "spi-controller.yaml#"
0014
0015 properties:
0016   compatible:
0017     oneOf:
0018       - enum:
0019           - fsl,vf610-qspi
0020           - fsl,imx6sx-qspi
0021           - fsl,imx7d-qspi
0022           - fsl,imx6ul-qspi
0023           - fsl,ls1021a-qspi
0024           - fsl,ls2080a-qspi
0025       - items:
0026           - enum:
0027               - fsl,ls1043a-qspi
0028           - const: fsl,ls1021a-qspi
0029       - items:
0030           - enum:
0031               - fsl,imx8mq-qspi
0032           - const: fsl,imx7d-qspi
0033
0034   reg:
0035     items:
0036       - description: registers
0037       - description: memory mapping
0038
0039   reg-names:
0040     items:
0041       - const: QuadSPI
0042       - const: QuadSPI-memory
0043
0044   interrupts:
0045     maxItems: 1
0046
0047   clocks:
0048     items:
0049       - description: SoC SPI qspi_en clock
0050       - description: SoC SPI qspi clock
0051
0052   clock-names:
0053     items:
0054       - const: qspi_en
0055       - const: qspi
0056
0057 required:
0058   - compatible
0059   - reg
0060   - reg-names
0061   - interrupts
0062   - clocks
0063   - clock-names
0064
0065 unevaluatedProperties: false
0066
0067 examples:
0068   - |
0069     #include <dt-bindings/interrupt-controller/arm-gic.h>
0070     #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
0071
0072     soc {
0073         #address-cells = <2>;
0074         #size-cells = <2>;
0075
0076         spi@1550000 {
0077             compatible = "fsl,ls1021a-qspi";
0078             reg = <0x0 0x1550000 0x0 0x100000>,
0079                   <0x0 0x40000000 0x0 0x10000000>;
0080             reg-names = "QuadSPI", "QuadSPI-memory";
0081             interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0082             #address-cells = <1>;
0083             #size-cells = <0>;
0084             clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>,
0085                      <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>;
0086             clock-names = "qspi_en", "qspi";
0087
0088             flash@0 {
0089                 compatible = "jedec,spi-nor";
0090                 spi-max-frequency = <50000000>;
0091                 reg = <0>;
0092                 spi-rx-bus-width = <4>;
0093                 spi-tx-bus-width = <4>;
0094             };
0095         };
0096     };