0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 # Copyright 2020-21 Cadence
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/spi/cdns,xspi.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: Cadence XSPI Controller
0009
0010 maintainers:
0011 - Parshuram Thombare <pthombar@cadence.com>
0012
0013 description: |
0014 The XSPI controller allows SPI protocol communication in
0015 single, dual, quad or octal wire transmission modes for
0016 read/write access to slaves such as SPI-NOR flash.
0017
0018 allOf:
0019 - $ref: "spi-controller.yaml#"
0020
0021 properties:
0022 compatible:
0023 const: cdns,xspi-nor
0024
0025 reg:
0026 items:
0027 - description: address and length of the controller register set
0028 - description: address and length of the Slave DMA data port
0029 - description: address and length of the auxiliary registers
0030
0031 reg-names:
0032 items:
0033 - const: io
0034 - const: sdma
0035 - const: aux
0036
0037 interrupts:
0038 maxItems: 1
0039
0040 required:
0041 - compatible
0042 - reg
0043 - interrupts
0044
0045 unevaluatedProperties: false
0046
0047 examples:
0048 - |
0049 #include <dt-bindings/interrupt-controller/irq.h>
0050 bus {
0051 #address-cells = <2>;
0052 #size-cells = <2>;
0053
0054 xspi: spi@a0010000 {
0055 #address-cells = <1>;
0056 #size-cells = <0>;
0057 compatible = "cdns,xspi-nor";
0058 reg = <0x0 0xa0010000 0x0 0x1040>,
0059 <0x0 0xb0000000 0x0 0x1000>,
0060 <0x0 0xa0020000 0x0 0x100>;
0061 reg-names = "io", "sdma", "aux";
0062 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
0063 interrupt-parent = <&gic>;
0064
0065 flash@0 {
0066 compatible = "jedec,spi-nor";
0067 spi-max-frequency = <75000000>;
0068 reg = <0>;
0069 };
0070
0071 flash@1 {
0072 compatible = "jedec,spi-nor";
0073 spi-max-frequency = <75000000>;
0074 reg = <1>;
0075 };
0076 };
0077 };
