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0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: Cadence Quad SPI controller
0008 
0009 maintainers:
0010   - Vaishnav Achath <vaishnav.a@ti.com>
0011 
0012 allOf:
0013   - $ref: spi-controller.yaml#
0014   - if:
0015       properties:
0016         compatible:
0017           contains:
0018             const: xlnx,versal-ospi-1.0
0019     then:
0020       required:
0021         - power-domains
0022 
0023 properties:
0024   compatible:
0025     oneOf:
0026       - items:
0027           - enum:
0028               - ti,k2g-qspi
0029               - ti,am654-ospi
0030               - intel,lgm-qspi
0031               - xlnx,versal-ospi-1.0
0032               - intel,socfpga-qspi
0033           - const: cdns,qspi-nor
0034       - const: cdns,qspi-nor
0035 
0036   reg:
0037     items:
0038       - description: the controller register set
0039       - description: the controller data area
0040 
0041   interrupts:
0042     maxItems: 1
0043 
0044   clocks:
0045     maxItems: 1
0046 
0047   cdns,fifo-depth:
0048     description:
0049       Size of the data FIFO in words.
0050     $ref: "/schemas/types.yaml#/definitions/uint32"
0051     enum: [ 128, 256 ]
0052     default: 128
0053 
0054   cdns,fifo-width:
0055     $ref: /schemas/types.yaml#/definitions/uint32
0056     description:
0057       Bus width of the data FIFO in bytes.
0058     default: 4
0059 
0060   cdns,trigger-address:
0061     $ref: /schemas/types.yaml#/definitions/uint32
0062     description:
0063       32-bit indirect AHB trigger address.
0064 
0065   cdns,is-decoded-cs:
0066     type: boolean
0067     description:
0068       Flag to indicate whether decoder is used to select different chip select
0069       for different memory regions.
0070 
0071   cdns,rclk-en:
0072     type: boolean
0073     description:
0074       Flag to indicate that QSPI return clock is used to latch the read
0075       data rather than the QSPI clock. Make sure that QSPI return clock
0076       is populated on the board before using this property.
0077 
0078   power-domains:
0079     maxItems: 1
0080 
0081   resets:
0082     maxItems: 2
0083 
0084   reset-names:
0085     minItems: 1
0086     maxItems: 2
0087     items:
0088       enum: [ qspi, qspi-ocp ]
0089 
0090 required:
0091   - compatible
0092   - reg
0093   - interrupts
0094   - clocks
0095   - cdns,fifo-depth
0096   - cdns,fifo-width
0097   - cdns,trigger-address
0098   - '#address-cells'
0099   - '#size-cells'
0100 
0101 unevaluatedProperties: false
0102 
0103 examples:
0104   - |
0105     qspi: spi@ff705000 {
0106       compatible = "cdns,qspi-nor";
0107       #address-cells = <1>;
0108       #size-cells = <0>;
0109       reg = <0xff705000 0x1000>,
0110             <0xffa00000 0x1000>;
0111       interrupts = <0 151 4>;
0112       clocks = <&qspi_clk>;
0113       cdns,fifo-depth = <128>;
0114       cdns,fifo-width = <4>;
0115       cdns,trigger-address = <0x00000000>;
0116       resets = <&rst 0x1>, <&rst 0x2>;
0117       reset-names = "qspi", "qspi-ocp";
0118 
0119       flash@0 {
0120               compatible = "jedec,spi-nor";
0121               reg = <0x0>;
0122       };
0123     };