0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Broadcom SPI controller
0008
0009 maintainers:
0010 - Kamal Dasu <kdasu.kdev@gmail.com>
0011 - Rafał Miłecki <rafal@milecki.pl>
0012
0013 description: |
0014 The Broadcom SPI controller is a SPI master found on various SOCs, including
0015 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
0016 of:
0017 MSPI : SPI master controller can read and write to a SPI slave device
0018 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
0019 for flash reads and be configured to do single, double, quad lane
0020 io with 3-byte and 4-byte addressing support.
0021
0022 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
0023 MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance
0024 of a MSPI master without the BSPI to use with non flash slave devices that
0025 use SPI protocol.
0026
0027 allOf:
0028 - $ref: spi-controller.yaml#
0029
0030 properties:
0031 compatible:
0032 oneOf:
0033 - description: Second Instance of MSPI BRCMSTB SoCs
0034 items:
0035 - enum:
0036 - brcm,spi-bcm7425-qspi
0037 - brcm,spi-bcm7429-qspi
0038 - brcm,spi-bcm7435-qspi
0039 - brcm,spi-bcm7445-qspi
0040 - brcm,spi-bcm7216-qspi
0041 - brcm,spi-bcm7278-qspi
0042 - const: brcm,spi-bcm-qspi
0043 - const: brcm,spi-brcmstb-mspi
0044 - description: Second Instance of MSPI BRCMSTB SoCs
0045 items:
0046 - enum:
0047 - brcm,spi-brcmstb-qspi
0048 - brcm,spi-brcmstb-mspi
0049 - brcm,spi-nsp-qspi
0050 - brcm,spi-ns2-qspi
0051 - const: brcm,spi-bcm-qspi
0052
0053 reg:
0054 minItems: 1
0055 maxItems: 5
0056
0057 reg-names:
0058 minItems: 1
0059 items:
0060 - const: mspi
0061 - const: bspi
0062 - enum: [ intr_regs, intr_status_reg, cs_reg ]
0063 - enum: [ intr_regs, intr_status_reg, cs_reg ]
0064 - enum: [ intr_regs, intr_status_reg, cs_reg ]
0065
0066 interrupts:
0067 minItems: 1
0068 maxItems: 7
0069
0070 interrupt-names:
0071 oneOf:
0072 - minItems: 1
0073 items:
0074 - const: mspi_done
0075 - const: mspi_halted
0076 - const: spi_lr_fullness_reached
0077 - const: spi_lr_session_aborted
0078 - const: spi_lr_impatient
0079 - const: spi_lr_session_done
0080 - const: spi_lr_overread
0081 - const: spi_l1_intr
0082
0083 clocks:
0084 maxItems: 1
0085 description: reference clock for this block
0086
0087 native-endian:
0088 $ref: /schemas/types.yaml#/definitions/flag
0089 description: Defined when using BE SoC and device uses BE register read/write
0090
0091 unevaluatedProperties: false
0092
0093 required:
0094 - reg
0095 - reg-names
0096 - interrupts
0097 - interrupt-names
0098
0099 examples:
0100 - | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access
0101 spi@f03e3400 {
0102 compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
0103 reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
0104 reg-names = "mspi", "bspi", "cs_reg";
0105 interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
0106 interrupt-parent = <&gic>;
0107 interrupt-names = "mspi_done",
0108 "mspi_halted",
0109 "spi_lr_fullness_reached",
0110 "spi_lr_session_aborted",
0111 "spi_lr_impatient",
0112 "spi_lr_session_done",
0113 "spi_lr_overread";
0114 clocks = <&hif_spi>;
0115 #address-cells = <0x1>;
0116 #size-cells = <0x0>;
0117
0118 flash@0 {
0119 #size-cells = <0x2>;
0120 #address-cells = <0x2>;
0121 compatible = "m25p80";
0122 reg = <0x0>;
0123 spi-max-frequency = <0x2625a00>;
0124 spi-cpol;
0125 spi-cpha;
0126 };
0127 };
0128 - | # BRCMSTB SoC: MSPI master for any SPI device
0129 spi@f0416000 {
0130 clocks = <&upg_fixed>;
0131 compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
0132 reg = <0xf0416000 0x180>;
0133 reg-names = "mspi";
0134 interrupts = <0x14>;
0135 interrupt-parent = <&irq0_aon_intc>;
0136 interrupt-names = "mspi_done";
0137 #address-cells = <1>;
0138 #size-cells = <0>;
0139 };
0140 - | # iProc SoC
0141 #include <dt-bindings/interrupt-controller/irq.h>
0142 #include <dt-bindings/interrupt-controller/arm-gic.h>
0143
0144 spi@18027200 {
0145 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
0146 reg = <0x18027200 0x184>,
0147 <0x18027000 0x124>,
0148 <0x1811c408 0x004>,
0149 <0x180273a0 0x01c>;
0150 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
0151 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
0152 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0154 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
0156 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
0157 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0158 interrupt-names = "mspi_done",
0159 "mspi_halted",
0160 "spi_lr_fullness_reached",
0161 "spi_lr_session_aborted",
0162 "spi_lr_impatient",
0163 "spi_lr_session_done";
0164 clocks = <&iprocmed>;
0165 num-cs = <2>;
0166 #address-cells = <1>;
0167 #size-cells = <0>;
0168 };
0169 - | # NS2 SoC
0170 #include <dt-bindings/interrupt-controller/irq.h>
0171 #include <dt-bindings/interrupt-controller/arm-gic.h>
0172
0173 spi@66470200 {
0174 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
0175 reg = <0x66470200 0x184>,
0176 <0x66470000 0x124>,
0177 <0x67017408 0x004>,
0178 <0x664703a0 0x01c>;
0179 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
0180 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
0181 interrupt-names = "spi_l1_intr";
0182 clocks = <&iprocmed>;
0183 num-cs = <2>;
0184 #address-cells = <1>;
0185 #size-cells = <0>;
0186
0187 flash@0 {
0188 #address-cells = <1>;
0189 #size-cells = <1>;
0190 compatible = "m25p80";
0191 reg = <0x0>;
0192 spi-max-frequency = <12500000>;
0193 spi-cpol;
0194 spi-cpha;
0195 };
0196 };
