0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/spi/atmel,at91rm9200-spi.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Atmel SPI device
0009
0010 maintainers:
0011 - Tudor Ambarus <tudor.ambarus@microchip.com>
0012
0013 allOf:
0014 - $ref: spi-controller.yaml#
0015
0016 properties:
0017 compatible:
0018 oneOf:
0019 - const: atmel,at91rm9200-spi
0020 - items:
0021 - const: microchip,sam9x60-spi
0022 - const: atmel,at91rm9200-spi
0023
0024 reg:
0025 maxItems: 1
0026
0027 interrupts:
0028 maxItems: 1
0029
0030 clock-names:
0031 contains:
0032 const: spi_clk
0033
0034 clocks:
0035 maxItems: 1
0036
0037 atmel,fifo-size:
0038 $ref: /schemas/types.yaml#/definitions/uint32
0039 description: |
0040 Maximum number of data the RX and TX FIFOs can store for FIFO
0041 capable SPI controllers.
0042 enum: [ 16, 32 ]
0043
0044 required:
0045 - compatible
0046 - reg
0047 - interrupts
0048 - clock-names
0049 - clocks
0050
0051 unevaluatedProperties: false
0052
0053 examples:
0054 - |
0055 #include <dt-bindings/gpio/gpio.h>
0056 #include <dt-bindings/interrupt-controller/irq.h>
0057
0058 spi1: spi@fffcc000 {
0059 compatible = "atmel,at91rm9200-spi";
0060 reg = <0xfffcc000 0x4000>;
0061 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
0062 #address-cells = <1>;
0063 #size-cells = <0>;
0064 clocks = <&spi1_clk>;
0065 clock-names = "spi_clk";
0066 cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
0067 atmel,fifo-size = <32>;
0068
0069 mmc@0 {
0070 compatible = "mmc-spi-slot";
0071 reg = <0>;
0072 gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; /* CD */
0073 spi-max-frequency = <25000000>;
0074 };
0075 };
