0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Aspeed SMC controllers bindings
0008
0009 maintainers:
0010 - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
0011 - Cédric Le Goater <clg@kaod.org>
0012
0013 description: |
0014 This binding describes the Aspeed Static Memory Controllers (FMC and
0015 SPI) of the AST2400, AST2500 and AST2600 SOCs.
0016
0017 allOf:
0018 - $ref: "spi-controller.yaml#"
0019
0020 properties:
0021 compatible:
0022 enum:
0023 - aspeed,ast2600-fmc
0024 - aspeed,ast2600-spi
0025 - aspeed,ast2500-fmc
0026 - aspeed,ast2500-spi
0027 - aspeed,ast2400-fmc
0028 - aspeed,ast2400-spi
0029
0030 reg:
0031 items:
0032 - description: registers
0033 - description: memory mapping
0034
0035 clocks:
0036 maxItems: 1
0037
0038 interrupts:
0039 maxItems: 1
0040
0041 required:
0042 - compatible
0043 - reg
0044 - clocks
0045
0046 unevaluatedProperties: false
0047
0048 examples:
0049 - |
0050 #include <dt-bindings/interrupt-controller/arm-gic.h>
0051 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
0052 #include <dt-bindings/clock/ast2600-clock.h>
0053
0054 spi@1e620000 {
0055 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
0056 #address-cells = <1>;
0057 #size-cells = <0>;
0058 compatible = "aspeed,ast2600-fmc";
0059 clocks = <&syscon ASPEED_CLK_AHB>;
0060 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0061
0062 flash@0 {
0063 reg = < 0 >;
0064 compatible = "jedec,spi-nor";
0065 spi-max-frequency = <50000000>;
0066 spi-rx-bus-width = <2>;
0067 };
0068
0069 flash@1 {
0070 reg = < 1 >;
0071 compatible = "jedec,spi-nor";
0072 spi-max-frequency = <50000000>;
0073 spi-rx-bus-width = <2>;
0074 };
0075
0076 flash@2 {
0077 reg = < 2 >;
0078 compatible = "jedec,spi-nor";
0079 spi-max-frequency = <50000000>;
0080 spi-rx-bus-width = <2>;
0081 };
0082 };
