0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/sound/mt8186-afe-pcm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek AFE PCM controller for mt8186
0008
0009 maintainers:
0010 - Jiaxin Yu <jiaxin.yu@mediatek.com>
0011
0012 properties:
0013 compatible:
0014 const: mediatek,mt8186-sound
0015
0016 reg:
0017 maxItems: 1
0018
0019 interrupts:
0020 maxItems: 1
0021
0022 resets:
0023 maxItems: 1
0024
0025 reset-names:
0026 const: audiosys
0027
0028 mediatek,apmixedsys:
0029 $ref: "/schemas/types.yaml#/definitions/phandle"
0030 description: The phandle of the mediatek apmixedsys controller
0031
0032 mediatek,infracfg:
0033 $ref: "/schemas/types.yaml#/definitions/phandle"
0034 description: The phandle of the mediatek infracfg controller
0035
0036 mediatek,topckgen:
0037 $ref: "/schemas/types.yaml#/definitions/phandle"
0038 description: The phandle of the mediatek topckgen controller
0039
0040 clocks:
0041 items:
0042 - description: audio infra sys clock
0043 - description: audio infra 26M clock
0044 - description: audio top mux
0045 - description: audio intbus mux
0046 - description: mainpll 136.5M clock
0047 - description: faud1 mux
0048 - description: apll1 clock
0049 - description: faud2 mux
0050 - description: apll2 clock
0051 - description: audio engen1 mux
0052 - description: apll1_d8 22.5792M clock
0053 - description: audio engen2 mux
0054 - description: apll2_d8 24.576M clock
0055 - description: i2s0 mclk mux
0056 - description: i2s1 mclk mux
0057 - description: i2s2 mclk mux
0058 - description: i2s4 mclk mux
0059 - description: tdm mclk mux
0060 - description: i2s0_mck divider
0061 - description: i2s1_mck divider
0062 - description: i2s2_mck divider
0063 - description: i2s4_mck divider
0064 - description: tdm_mck divider
0065 - description: audio hires mux
0066 - description: 26M clock
0067
0068 clock-names:
0069 items:
0070 - const: aud_infra_clk
0071 - const: mtkaif_26m_clk
0072 - const: top_mux_audio
0073 - const: top_mux_audio_int
0074 - const: top_mainpll_d2_d4
0075 - const: top_mux_aud_1
0076 - const: top_apll1_ck
0077 - const: top_mux_aud_2
0078 - const: top_apll2_ck
0079 - const: top_mux_aud_eng1
0080 - const: top_apll1_d8
0081 - const: top_mux_aud_eng2
0082 - const: top_apll2_d8
0083 - const: top_i2s0_m_sel
0084 - const: top_i2s1_m_sel
0085 - const: top_i2s2_m_sel
0086 - const: top_i2s4_m_sel
0087 - const: top_tdm_m_sel
0088 - const: top_apll12_div0
0089 - const: top_apll12_div1
0090 - const: top_apll12_div2
0091 - const: top_apll12_div4
0092 - const: top_apll12_div_tdm
0093 - const: top_mux_audio_h
0094 - const: top_clk26m_clk
0095
0096 required:
0097 - compatible
0098 - interrupts
0099 - resets
0100 - reset-names
0101 - mediatek,apmixedsys
0102 - mediatek,infracfg
0103 - mediatek,topckgen
0104 - clocks
0105 - clock-names
0106
0107 additionalProperties: false
0108
0109 examples:
0110 - |
0111 #include <dt-bindings/interrupt-controller/arm-gic.h>
0112 #include <dt-bindings/interrupt-controller/irq.h>
0113
0114 afe: mt8186-afe-pcm@11210000 {
0115 compatible = "mediatek,mt8186-sound";
0116 reg = <0x11210000 0x2000>;
0117 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
0118 resets = <&watchdog 17>; //MT8186_TOPRGU_AUDIO_SW_RST
0119 reset-names = "audiosys";
0120 mediatek,apmixedsys = <&apmixedsys>;
0121 mediatek,infracfg = <&infracfg>;
0122 mediatek,topckgen = <&topckgen>;
0123 clocks = <&infracfg_ao 44>, //CLK_INFRA_AO_AUDIO
0124 <&infracfg_ao 54>, //CLK_INFRA_AO_AUDIO_26M_BCLK
0125 <&topckgen 15>, //CLK_TOP_AUDIO
0126 <&topckgen 16>, //CLK_TOP_AUD_INTBUS
0127 <&topckgen 70>, //CLK_TOP_MAINPLL_D2_D4
0128 <&topckgen 17>, //CLK_TOP_AUD_1
0129 <&apmixedsys 12>, //CLK_APMIXED_APLL1
0130 <&topckgen 18>, //CLK_TOP_AUD_2
0131 <&apmixedsys 13>, //CLK_APMIXED_APLL2
0132 <&topckgen 19>, //CLK_TOP_AUD_ENGEN1
0133 <&topckgen 101>, //CLK_TOP_APLL1_D8
0134 <&topckgen 20>, //CLK_TOP_AUD_ENGEN2
0135 <&topckgen 104>, //CLK_TOP_APLL2_D8
0136 <&topckgen 63>, //CLK_TOP_APLL_I2S0_MCK_SEL
0137 <&topckgen 64>, //CLK_TOP_APLL_I2S1_MCK_SEL
0138 <&topckgen 65>, //CLK_TOP_APLL_I2S2_MCK_SEL
0139 <&topckgen 66>, //CLK_TOP_APLL_I2S4_MCK_SEL
0140 <&topckgen 67>, //CLK_TOP_APLL_TDMOUT_MCK_SEL
0141 <&topckgen 131>, //CLK_TOP_APLL12_CK_DIV0
0142 <&topckgen 132>, //CLK_TOP_APLL12_CK_DIV1
0143 <&topckgen 133>, //CLK_TOP_APLL12_CK_DIV2
0144 <&topckgen 134>, //CLK_TOP_APLL12_CK_DIV4
0145 <&topckgen 135>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M
0146 <&topckgen 44>, //CLK_TOP_AUDIO_H
0147 <&clk26m>;
0148 clock-names = "aud_infra_clk",
0149 "mtkaif_26m_clk",
0150 "top_mux_audio",
0151 "top_mux_audio_int",
0152 "top_mainpll_d2_d4",
0153 "top_mux_aud_1",
0154 "top_apll1_ck",
0155 "top_mux_aud_2",
0156 "top_apll2_ck",
0157 "top_mux_aud_eng1",
0158 "top_apll1_d8",
0159 "top_mux_aud_eng2",
0160 "top_apll2_d8",
0161 "top_i2s0_m_sel",
0162 "top_i2s1_m_sel",
0163 "top_i2s2_m_sel",
0164 "top_i2s4_m_sel",
0165 "top_tdm_m_sel",
0166 "top_apll12_div0",
0167 "top_apll12_div1",
0168 "top_apll12_div2",
0169 "top_apll12_div4",
0170 "top_apll12_div_tdm",
0171 "top_mux_audio_h",
0172 "top_clk26m_clk";
0173 };
0174
0175 ...
