soc/xilinx/xlnx%2Cvcu.txt

0001 LogicoreIP designed compatible with Xilinx ZYNQ family.
0002 -------------------------------------------------------
0003
0004 General concept
0005 ---------------
0006
0007 LogicoreIP design to provide the isolation between processing system
0008 and programmable logic. Also provides the list of register set to configure
0009 the frequency.
0010
0011 Required properties:
0012 - compatible: shall be one of:
0013         "xlnx,vcu"
0014         "xlnx,vcu-logicoreip-1.0"
0015 - reg : The base offset and size of the VCU_PL_SLCR register space.
0016 - clocks: phandle for aclk and pll_ref clocksource
0017 - clock-names: The identification string, "aclk", is always required for
0018    the axi clock. "pll_ref" is required for pll.
0019 Example:
0020
0021         xlnx_vcu: vcu@a0040000 {
0022                 compatible = "xlnx,vcu-logicoreip-1.0";
0023                 reg = <0x0 0xa0040000 0x0 0x1000>;
0024                 clocks = <&si570_1>, <&clkc 71>;
0025                 clock-names = "pll_ref", "aclk";
0026         };