0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Wakeup M3 IPC device
0008
0009 maintainers:
0010 - Dave Gerlach <d-gerlach@ti.com>
0011 - Drew Fustini <dfustini@baylibre.com>
0012
0013 description: |+
0014 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
0015 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
0016 that cannot be controlled from the MPU, like suspend/resume and certain deep
0017 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
0018 to boot the wkup_m3, it handles communication with the CM3 using IPC registers
0019 present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an
0020 API to allow the SoC PM code to execute specific PM tasks.
0021
0022 Wkup M3 Device Node
0023 ====================
0024 A wkup_m3_ipc device node is used to represent the IPC registers within an
0025 SoC.
0026
0027 Support for VTT Toggle with GPIO pin
0028 ====================================
0029 On some boards like the AM335x EVM-SK and the AM437x GP EVM, a GPIO pin is
0030 connected to the enable pin on the DDR VTT regulator. This allows the
0031 regulator to be disabled upon suspend and enabled upon resume. Please note
0032 that the GPIO pin must be part of the GPIO0 module as only this GPIO module
0033 is in the wakeup power domain.
0034
0035 Support for IO Isolation
0036 ========================
0037 On AM437x SoCs, certain pins can be forced into an alternate state when IO
0038 isolation is activated. Those pins have pad control registers prefixed by
0039 'CTRL_CONF_' that contain DS0 (e.g. deep sleep) configuration bits that can
0040 override the pin's existing bias (pull-up/pull-down) and value (high/low) when
0041 IO isolation is active.
0042
0043 Support for I2C PMIC Voltage Scaling
0044 ====================================
0045 It is possible to pass the name of a binary file to load into the CM3 memory.
0046 The binary data is the I2C sequences for the CM3 to send out to the PMIC
0047 during low power mode entry.
0048
0049 properties:
0050 compatible:
0051 enum:
0052 - ti,am3352-wkup-m3-ipc # for AM33xx SoCs
0053 - ti,am4372-wkup-m3-ipc # for AM43xx SoCs
0054
0055 reg:
0056 description:
0057 The IPC register address space to communicate with the Wakeup M3 processor
0058 maxItems: 1
0059
0060 interrupts:
0061 description: wkup_m3 interrupt that signals the MPU
0062 maxItems: 1
0063
0064 ti,rproc:
0065 $ref: /schemas/types.yaml#/definitions/phandle
0066 description:
0067 phandle to the wkup_m3 rproc node so the IPC driver can boot it
0068
0069 mboxes:
0070 description:
0071 phandles used by IPC framework to get correct mbox
0072 channel for communication. Must point to appropriate
0073 mbox_wkupm3 child node.
0074 maxItems: 1
0075
0076 firmware-name:
0077 description:
0078 Name of binary file with I2C sequences for PMIC voltage scaling
0079
0080 ti,vtt-gpio-pin:
0081 $ref: /schemas/types.yaml#/definitions/uint32
0082 description: GPIO pin connected to enable pin on VTT regulator
0083
0084 ti,set-io-isolation:
0085 type: boolean
0086 description:
0087 If this property is present, then the wkup_m3_ipc driver will instruct
0088 the CM3 firmware to activate IO isolation when suspending to deep sleep.
0089 This can be leveraged by a board design to put other devices on the board
0090 into a low power state.
0091
0092 allOf:
0093 - if:
0094 properties:
0095 compatible:
0096 not:
0097 contains:
0098 const: ti,am4372-wkup-m3-ipc
0099 then:
0100 properties:
0101 ti,set-io-isolation: false
0102
0103 required:
0104 - compatible
0105 - reg
0106 - interrupts
0107 - ti,rproc
0108 - mboxes
0109
0110 additionalProperties: false
0111
0112 examples:
0113 - |
0114 /* Example for AM335x SoC */
0115 soc {
0116 #address-cells = <1>;
0117 #size-cells = <1>;
0118
0119 am335x_mailbox: mailbox {
0120 #mbox-cells = <1>;
0121 };
0122
0123 wkup_m3_ipc@1324 {
0124 compatible = "ti,am3352-wkup-m3-ipc";
0125 reg = <0x1324 0x24>;
0126 interrupts = <78>;
0127 ti,rproc = <&wkup_m3>;
0128 mboxes = <&am335x_mailbox &mbox_wkupm3>;
0129 ti,vtt-gpio-pin = <7>;
0130 firmware-name = "am335x-evm-scale-data.bin";
0131 };
0132 };
0133
0134 - |
0135 /*
0136 * Example for AM473x SoC:
0137 * On the AM437x-GP-EVM board, gpio5_7 is wired to enable pin of the DDR VTT
0138 * regulator. The 'ddr_vtt_toggle_default' pinmux node configures gpio5_7
0139 * for pull-up during normal system operation. However, the DS0 (deep sleep)
0140 * state of the pin is configured for pull-down and thus the VTT regulator
0141 * will be disabled to save power when IO isolation is active. Note that
0142 * this method is an alternative to using the 'ti,vtt-gpio-pin' property.
0143 */
0144 #include <dt-bindings/pinctrl/am43xx.h>
0145 soc {
0146 #address-cells = <1>;
0147 #size-cells = <1>;
0148
0149 am437x_mailbox: mailbox {
0150 #mbox-cells = <1>;
0151 };
0152
0153 am43xx_pinmux {
0154 pinctrl-names = "default";
0155 pinctrl-0 = <&ddr3_vtt_toggle_default>;
0156
0157 ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
0158 pinctrl-single,pins = <
0159 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7)
0160 >;
0161 };
0162 };
0163
0164 wkup_m3_ipc@1324 {
0165 compatible = "ti,am4372-wkup-m3-ipc";
0166 reg = <0x1324 0x24>;
0167 interrupts = <78>;
0168 ti,rproc = <&wkup_m3>;
0169 mboxes = <&am437x_mailbox &mbox_wkupm3>;
0170 ti,set-io-isolation;
0171 firmware-name = "am43x-evm-scale-data.bin";
0172 };
0173 };
0174
0175 ...
