0001 * Texas Instruments Keystone Navigator Queue Management SubSystem driver
0002
0003 The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
0004 the main hardware sub system which forms the backbone of the Keystone
0005 multi-core Navigator. QMSS consist of queue managers, packed-data structure
0006 processors(PDSP), linking RAM, descriptor pools and infrastructure
0007 Packet DMA.
0008 The Queue Manager is a hardware module that is responsible for accelerating
0009 management of the packet queues. Packets are queued/de-queued by writing or
0010 reading descriptor address to a particular memory mapped location. The PDSPs
0011 perform QMSS related functions like accumulation, QoS, or event management.
0012 Linking RAM registers are used to link the descriptors which are stored in
0013 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
0014 The QMSS driver manages the PDSP setups, linking RAM regions,
0015 queue pool management (allocation, push, pop and notify) and descriptor
0016 pool management.
0017
0018
0019 Required properties:
0020 - compatible : Must be "ti,keystone-navigator-qmss".
0021 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
0022 - clocks : phandle to the reference clock for this device.
0023 - queue-range : <start number> total range of queue numbers for the device.
0024 - linkram0 : <address size> for internal link ram, where size is the total
0025 link ram entries.
0026 - linkram1 : <address size> for external link ram, where size is the total
0027 external link ram entries. If the address is specified as "0"
0028 driver will allocate memory.
0029 - qmgrs : child node describing the individual queue managers on the
0030 SoC. On keystone 1 devices there should be only one node.
0031 On keystone 2 devices there can be more than 1 node.
0032 -- managed-queues : the actual queues managed by each queue manager
0033 instance, specified as <"base queue #" "# of queues">.
0034 -- reg : Address and size of the register set for the device.
0035 Register regions should be specified in the following
0036 order
0037 - Queue Peek region.
0038 - Queue status RAM.
0039 - Queue configuration region.
0040 - Descriptor memory setup region.
0041 - Queue Management/Queue Proxy region for queue Push.
0042 - Queue Management/Queue Proxy region for queue Pop.
0043
0044 For QMSS on K2G SoC, following QM reg indexes are used in that order
0045 - Queue Peek region.
0046 - Queue configuration region.
0047 - Queue Management/Queue Proxy region for queue Push/Pop.
0048
0049 - queue-pools : child node classifying the queue ranges into pools.
0050 Queue ranges are grouped into 3 type of pools:
0051 - qpend : pool of qpend(interruptible) queues
0052 - general-purpose : pool of general queues, primarily used
0053 as free descriptor queues or the
0054 transmit DMA queues.
0055 - accumulator : pool of queues on PDSP accumulator channel
0056 Each range can have the following properties:
0057 -- qrange : number of queues to use per queue range, specified as
0058 <"base queue #" "# of queues">.
0059 -- interrupts : Optional property to specify the interrupt mapping
0060 for interruptible queues. The driver additionally sets
0061 the interrupt affinity hint based on the cpu mask.
0062 -- qalloc-by-id : Optional property to specify that the queues in this
0063 range can only be allocated by queue id.
0064 -- accumulator : Accumulator channel specification. Any of the PDSPs in
0065 QMSS can be loaded with the accumulator firmware. The
0066 accumulator firmware’s job is to poll a select number of
0067 queues looking for descriptors that have been pushed
0068 into them. Descriptors are popped from the queue and
0069 placed in a buffer provided by the host. When the list
0070 becomes full or a programmed time period expires, the
0071 accumulator triggers an interrupt to the host to read
0072 the buffer for descriptor information. This firmware
0073 comes in 16, 32, and 48 channel builds. Each of these
0074 channels can be configured to monitor 32 contiguous
0075 queues. Accumulator channel property is specified as:
0076 <pdsp-id, channel, entries, pacing mode, latency>
0077 pdsp-id : QMSS PDSP running accumulator firmware
0078 on which the channel has to be
0079 configured
0080 channel : Accumulator channel number
0081 entries : Size of the accumulator descriptor list
0082 pacing mode : Interrupt pacing mode
0083 0 : None, i.e interrupt on list full only
0084 1 : Time delay since last interrupt
0085 2 : Time delay since first new packet
0086 3 : Time delay since last new packet
0087 latency : time to delay the interrupt, specified
0088 in microseconds.
0089 -- multi-queue : Optional property to specify that the channel has to
0090 monitor up to 32 queues starting at the base queue #.
0091 - descriptor-regions : child node describing the memory regions for keystone
0092 navigator packet DMA descriptors. The memory for
0093 descriptors will be allocated by the driver.
0094 -- id : region number in QMSS.
0095 -- region-spec : specifies the number of descriptors in the
0096 region, specified as
0097 <"# of descriptors" "descriptor size">.
0098 -- link-index : start index, i.e. index of the first
0099 descriptor in the region.
0100
0101 Optional properties:
0102 - dma-coherent : Present if DMA operations are coherent.
0103 - pdsps : child node describing the PDSP configuration.
0104 -- firmware : firmware to be loaded on the PDSP.
0105 -- id : the qmss pdsp that will run the firmware.
0106 -- reg : Address and size of the register set for the PDSP.
0107 Register regions should be specified in the following
0108 order
0109 - PDSP internal RAM region.
0110 - PDSP control/status region registers.
0111 - QMSS interrupt distributor registers.
0112 - PDSP command interface region.
0113
0114 Example:
0115
0116 qmss: qmss@2a40000 {
0117 compatible = "ti,keystone-qmss";
0118 dma-coherent;
0119 #address-cells = <1>;
0120 #size-cells = <1>;
0121 clocks = <&chipclk13>;
0122 ranges;
0123 queue-range = <0 0x4000>;
0124 linkram0 = <0x100000 0x8000>;
0125 linkram1 = <0x0 0x10000>;
0126
0127 qmgrs {
0128 #address-cells = <1>;
0129 #size-cells = <1>;
0130 ranges;
0131 qmgr0 {
0132 managed-queues = <0 0x2000>;
0133 reg = <0x2a40000 0x20000>,
0134 <0x2a06000 0x400>,
0135 <0x2a02000 0x1000>,
0136 <0x2a03000 0x1000>,
0137 <0x23a80000 0x20000>,
0138 <0x2a80000 0x20000>;
0139 };
0140
0141 qmgr1 {
0142 managed-queues = <0x2000 0x2000>;
0143 reg = <0x2a60000 0x20000>,
0144 <0x2a06400 0x400>,
0145 <0x2a04000 0x1000>,
0146 <0x2a05000 0x1000>,
0147 <0x23aa0000 0x20000>,
0148 <0x2aa0000 0x20000>;
0149 };
0150 };
0151 queue-pools {
0152 qpend {
0153 qpend-0 {
0154 qrange = <658 8>;
0155 interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
0156 0 43 0xf04 0 44 0xf04 0 45 0xf04
0157 0 46 0xf04 0 47 0xf04>;
0158 };
0159 qpend-1 {
0160 qrange = <8704 16>;
0161 interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
0162 0 51 0xf04 0 52 0xf04 0 53 0xf04
0163 0 54 0xf04 0 55 0xf04 0 56 0xf04
0164 0 57 0xf04 0 58 0xf04 0 59 0xf04
0165 0 60 0xf04 0 61 0xf04 0 62 0xf04
0166 0 63 0xf04>;
0167 qalloc-by-id;
0168 };
0169 qpend-2 {
0170 qrange = <8720 16>;
0171 interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
0172 0 59 0xf04 0 68 0xf04 0 69 0xf04
0173 0 70 0xf04 0 71 0xf04 0 72 0xf04
0174 0 73 0xf04 0 74 0xf04 0 75 0xf04
0175 0 76 0xf04 0 77 0xf04 0 78 0xf04
0176 0 79 0xf04>;
0177 };
0178 };
0179 general-purpose {
0180 gp-0 {
0181 qrange = <4000 64>;
0182 };
0183 netcp-tx {
0184 qrange = <640 9>;
0185 qalloc-by-id;
0186 };
0187 };
0188 accumulator {
0189 acc-0 {
0190 qrange = <128 32>;
0191 accumulator = <0 36 16 2 50>;
0192 interrupts = <0 215 0xf01>;
0193 multi-queue;
0194 qalloc-by-id;
0195 };
0196 acc-1 {
0197 qrange = <160 32>;
0198 accumulator = <0 37 16 2 50>;
0199 interrupts = <0 216 0xf01>;
0200 multi-queue;
0201 };
0202 acc-2 {
0203 qrange = <192 32>;
0204 accumulator = <0 38 16 2 50>;
0205 interrupts = <0 217 0xf01>;
0206 multi-queue;
0207 };
0208 acc-3 {
0209 qrange = <224 32>;
0210 accumulator = <0 39 16 2 50>;
0211 interrupts = <0 218 0xf01>;
0212 multi-queue;
0213 };
0214 };
0215 };
0216 descriptor-regions {
0217 #address-cells = <1>;
0218 #size-cells = <1>;
0219 ranges;
0220 region-12 {
0221 id = <12>;
0222 region-spec = <8192 128>; /* num_desc desc_size */
0223 link-index = <0x4000>;
0224 };
0225 };
0226 pdsps {
0227 #address-cells = <1>;
0228 #size-cells = <1>;
0229 ranges;
0230 pdsp0@2a10000 {
0231 reg = <0x2a10000 0x1000>,
0232 <0x2a0f000 0x100>,
0233 <0x2a0c000 0x3c8>,
0234 <0x2a20000 0x4000>;
0235 id = <0>;
0236 };
0237 };
0238 }; /* qmss */
