0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung's Exynos USI (Universal Serial Interface) binding
0008
0009 maintainers:
0010 - Sam Protsenko <semen.protsenko@linaro.org>
0011 - Krzysztof Kozlowski <krzk@kernel.org>
0012
0013 description: |
0014 USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
0015 USI shares almost all internal circuits within each protocol, so only one
0016 protocol can be chosen at a time. USI is modeled as a node with zero or more
0017 child nodes, each representing a serial sub-node device. The mode setting
0018 selects which particular function will be used.
0019
0020 properties:
0021 $nodename:
0022 pattern: "^usi@[0-9a-f]+$"
0023
0024 compatible:
0025 oneOf:
0026 - items:
0027 - const: samsung,exynosautov9-usi
0028 - const: samsung,exynos850-usi
0029 - enum:
0030 - samsung,exynos850-usi
0031
0032 reg: true
0033
0034 clocks: true
0035
0036 clock-names: true
0037
0038 ranges: true
0039
0040 "#address-cells":
0041 const: 1
0042
0043 "#size-cells":
0044 const: 1
0045
0046 samsung,sysreg:
0047 $ref: /schemas/types.yaml#/definitions/phandle-array
0048 items:
0049 - items:
0050 - description: phandle to System Register syscon node
0051 - description: offset of SW_CONF register for this USI controller
0052 description:
0053 Should be phandle/offset pair. The phandle to System Register syscon node
0054 (for the same domain where this USI controller resides) and the offset
0055 of SW_CONF register for this USI controller.
0056
0057 samsung,mode:
0058 $ref: /schemas/types.yaml#/definitions/uint32
0059 description:
0060 Selects USI function (which serial protocol to use). Refer to
0061 <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
0062
0063 samsung,clkreq-on:
0064 type: boolean
0065 description:
0066 Enable this property if underlying protocol requires the clock to be
0067 continuously provided without automatic gating. As suggested by SoC
0068 manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
0069 multi-master mode. Usually this property is needed if USI mode is set
0070 to "UART".
0071
0072 This property is optional.
0073
0074 patternProperties:
0075 "^i2c@[0-9a-f]+$":
0076 $ref: /schemas/i2c/i2c-exynos5.yaml
0077 description: Child node describing underlying I2C
0078
0079 "^serial@[0-9a-f]+$":
0080 $ref: /schemas/serial/samsung_uart.yaml
0081 description: Child node describing underlying UART/serial
0082
0083 "^spi@[0-9a-f]+$":
0084 $ref: /schemas/spi/samsung,spi.yaml
0085 description: Child node describing underlying SPI
0086
0087 required:
0088 - compatible
0089 - ranges
0090 - "#address-cells"
0091 - "#size-cells"
0092 - samsung,sysreg
0093 - samsung,mode
0094
0095 if:
0096 properties:
0097 compatible:
0098 contains:
0099 enum:
0100 - samsung,exynos850-usi
0101
0102 then:
0103 properties:
0104 reg:
0105 maxItems: 1
0106
0107 clocks:
0108 items:
0109 - description: Bus (APB) clock
0110 - description: Operating clock for UART/SPI/I2C protocol
0111
0112 clock-names:
0113 items:
0114 - const: pclk
0115 - const: ipclk
0116
0117 required:
0118 - reg
0119 - clocks
0120 - clock-names
0121
0122 else:
0123 properties:
0124 reg: false
0125 clocks: false
0126 clock-names: false
0127 samsung,clkreq-on: false
0128
0129 additionalProperties: false
0130
0131 examples:
0132 - |
0133 #include <dt-bindings/interrupt-controller/arm-gic.h>
0134 #include <dt-bindings/soc/samsung,exynos-usi.h>
0135
0136 usi0: usi@138200c0 {
0137 compatible = "samsung,exynos850-usi";
0138 reg = <0x138200c0 0x20>;
0139 samsung,sysreg = <&sysreg_peri 0x1010>;
0140 samsung,mode = <USI_V2_UART>;
0141 samsung,clkreq-on; /* needed for UART mode */
0142 #address-cells = <1>;
0143 #size-cells = <1>;
0144 ranges;
0145 clocks = <&cmu_peri 32>, <&cmu_peri 31>;
0146 clock-names = "pclk", "ipclk";
0147
0148 serial_0: serial@13820000 {
0149 compatible = "samsung,exynos850-uart";
0150 reg = <0x13820000 0xc0>;
0151 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
0152 clocks = <&cmu_peri 32>, <&cmu_peri 31>;
0153 clock-names = "uart", "clk_uart_baud0";
0154 status = "disabled";
0155 };
0156
0157 hsi2c_0: i2c@13820000 {
0158 compatible = "samsung,exynosautov9-hsi2c";
0159 reg = <0x13820000 0xc0>;
0160 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
0161 #address-cells = <1>;
0162 #size-cells = <0>;
0163 clocks = <&cmu_peri 31>, <&cmu_peri 32>;
0164 clock-names = "hsi2c", "hsi2c_pclk";
0165 status = "disabled";
0166 };
0167 };
