0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/soc/qcom/qcom,smsm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Shared Memory State Machine
0008
0009 maintainers:
0010 - Andy Gross <agross@kernel.org>
0011 - Bjorn Andersson <bjorn.andersson@linaro.org>
0012 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
0013
0014 description:
0015 The Shared Memory State Machine facilitates broadcasting of single bit state
0016 information between the processors in a Qualcomm SoC. Each processor is
0017 assigned 32 bits of state that can be modified. A processor can through a
0018 matrix of bitmaps signal subscription of notifications upon changes to a
0019 certain bit owned by a certain remote processor.
0020
0021 properties:
0022 compatible:
0023 const: qcom,smsm
0024
0025 '#address-cells':
0026 const: 1
0027
0028 qcom,local-host:
0029 $ref: /schemas/types.yaml#/definitions/uint32
0030 default: 0
0031 description:
0032 Identifier of the local processor in the list of hosts, or in other words
0033 specifier of the column in the subscription matrix representing the local
0034 processor.
0035
0036 '#size-cells':
0037 const: 0
0038
0039 patternProperties:
0040 "^qcom,ipc-[1-4]$":
0041 $ref: /schemas/types.yaml#/definitions/phandle-array
0042 items:
0043 - items:
0044 - description: phandle to a syscon node representing the APCS registers
0045 - description: u32 representing offset to the register within the syscon
0046 - description: u32 representing the ipc bit within the register
0047 description:
0048 Three entries specifying the outgoing ipc bit used for signaling the N:th
0049 remote processor.
0050
0051 "@[0-9a-f]$":
0052 type: object
0053 description:
0054 Each processor's state bits are described by a subnode of the SMSM device
0055 node. Nodes can either be flagged as an interrupt-controller to denote a
0056 remote processor's state bits or the local processors bits. The node
0057 names are not important.
0058
0059 properties:
0060 reg:
0061 maxItems: 1
0062
0063 interrupt-controller:
0064 description:
0065 Marks the entry as a interrupt-controller and the state bits to
0066 belong to a remote processor.
0067
0068 '#interrupt-cells':
0069 const: 2
0070
0071 interrupts:
0072 maxItems: 1
0073 description:
0074 One entry specifying remote IRQ used by the remote processor to
0075 signal changes of its state bits.
0076
0077 '#qcom,smem-state-cells':
0078 $ref: /schemas/types.yaml#/definitions/uint32
0079 const: 1
0080 description:
0081 Required for local entry. Denotes bit number.
0082
0083 required:
0084 - reg
0085
0086 oneOf:
0087 - required:
0088 - '#qcom,smem-state-cells'
0089 - required:
0090 - interrupt-controller
0091 - '#interrupt-cells'
0092 - interrupts
0093
0094 additionalProperties: false
0095
0096 required:
0097 - compatible
0098 - '#address-cells'
0099 - '#size-cells'
0100
0101 anyOf:
0102 - required:
0103 - qcom,ipc-1
0104 - required:
0105 - qcom,ipc-2
0106 - required:
0107 - qcom,ipc-3
0108 - required:
0109 - qcom,ipc-4
0110
0111 additionalProperties: false
0112
0113 examples:
0114 # The following example shows the SMEM setup for controlling properties of
0115 # the wireless processor, defined from the 8974 apps processor's
0116 # point-of-view. It encompasses one outbound entry and the outgoing interrupt
0117 # for the wireless processor.
0118 - |
0119 #include <dt-bindings/interrupt-controller/arm-gic.h>
0120
0121 shared-memory {
0122 compatible = "qcom,smsm";
0123 #address-cells = <1>;
0124 #size-cells = <0>;
0125 qcom,ipc-3 = <&apcs 8 19>;
0126
0127 apps_smsm: apps@0 {
0128 reg = <0>;
0129 #qcom,smem-state-cells = <1>;
0130 };
0131
0132 wcnss_smsm: wcnss@7 {
0133 reg = <7>;
0134 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
0135 interrupt-controller;
0136 #interrupt-cells = <2>;
0137 };
0138 };
