0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm RPMH RSC
0008
0009 maintainers:
0010 - Bjorn Andersson <bjorn.andersson@linaro.org>
0011
0012 description: |
0013 Resource Power Manager Hardened (RPMH) is the mechanism for communicating
0014 with the hardened resource accelerators on Qualcomm SoCs. Requests to the
0015 resources can be written to the Trigger Command Set (TCS) registers and
0016 using a (addr, val) pair and triggered. Messages in the TCS are then sent in
0017 sequence over an internal bus.
0018
0019 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
0020 (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
0021 active/wake resource requests. Multiple such DRVs can exist in a SoC and can
0022 be written to from Linux. The structure of each DRV follows the same template
0023 with a few variations that are captured by the properties here.
0024
0025 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
0026 have powered off to facilitate idle power saving. TCS could be classified as::
0027 ACTIVE - Triggered by Linux
0028 SLEEP - Triggered by F/W
0029 WAKE - Triggered by F/W
0030 CONTROL - Triggered by F/W
0031 See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
0032
0033 The order in which they are described in the DT, should match the hardware
0034 configuration.
0035
0036 Requests can be made for the state of a resource, when the subsystem is
0037 active or idle. When all subsystems like Modem, GPU, CPU are idle, the
0038 resource state will be an aggregate of the sleep votes from each of those
0039 subsystems. Clients may request a sleep value for their shared resources in
0040 addition to the active mode requests.
0041
0042 Drivers that want to use the RSC to communicate with RPMH must specify their
0043 bindings as child nodes of the RSC controllers they wish to communicate with.
0044
0045 properties:
0046 compatible:
0047 const: qcom,rpmh-rsc
0048
0049 interrupts:
0050 minItems: 1
0051 maxItems: 4
0052 description:
0053 The interrupt that trips when a message complete/response is received for
0054 this DRV from the accelerators.
0055 Number of interrupts must match number of DRV blocks.
0056
0057 label:
0058 description:
0059 Name for the RSC. The name would be used in trace logs.
0060
0061 qcom,drv-id:
0062 $ref: /schemas/types.yaml#/definitions/uint32
0063 description:
0064 The ID of the DRV in the RSC block that will be used by this controller.
0065
0066 qcom,tcs-config:
0067 $ref: /schemas/types.yaml#/definitions/uint32-matrix
0068 minItems: 4
0069 maxItems: 4
0070 items:
0071 items:
0072 - description: |
0073 TCS type::
0074 - ACTIVE_TCS
0075 - SLEEP_TCS
0076 - WAKE_TCS
0077 - CONTROL_TCS
0078 enum: [ 0, 1, 2, 3 ]
0079 - description: Number of TCS
0080 description: |
0081 The tuple defining the configuration of TCS. Must have two cells which
0082 describe each TCS type. The order of the TCS must match the hardware
0083 configuration.
0084
0085 qcom,tcs-offset:
0086 $ref: /schemas/types.yaml#/definitions/uint32
0087 description:
0088 The offset of the TCS blocks.
0089
0090 reg:
0091 minItems: 1
0092 maxItems: 4
0093
0094 reg-names:
0095 minItems: 1
0096 items:
0097 - const: drv-0
0098 - const: drv-1
0099 - const: drv-2
0100 - const: drv-3
0101
0102 bcm-voter:
0103 $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
0104
0105 clock-controller:
0106 $ref: /schemas/clock/qcom,rpmhcc.yaml#
0107
0108 power-controller:
0109 $ref: /schemas/power/qcom,rpmpd.yaml#
0110
0111 patternProperties:
0112 '-regulators$':
0113 $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
0114
0115 required:
0116 - compatible
0117 - interrupts
0118 - qcom,drv-id
0119 - qcom,tcs-config
0120 - qcom,tcs-offset
0121 - reg
0122 - reg-names
0123
0124 additionalProperties: false
0125
0126 examples:
0127 - |
0128 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
0129 // 2, the register offsets for DRV2 start at 0D00, the register
0130 // calculations are like this::
0131 // DRV0: 0x179C0000
0132 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
0133 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
0134 // TCS-OFFSET: 0xD00
0135 #include <dt-bindings/interrupt-controller/arm-gic.h>
0136 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
0137
0138 rsc@179c0000 {
0139 compatible = "qcom,rpmh-rsc";
0140 reg = <0x179c0000 0x10000>,
0141 <0x179d0000 0x10000>,
0142 <0x179e0000 0x10000>;
0143 reg-names = "drv-0", "drv-1", "drv-2";
0144 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0145 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0146 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0147 label = "apps_rsc";
0148 qcom,tcs-offset = <0xd00>;
0149 qcom,drv-id = <2>;
0150 qcom,tcs-config = <ACTIVE_TCS 2>,
0151 <SLEEP_TCS 3>,
0152 <WAKE_TCS 3>,
0153 <CONTROL_TCS 1>;
0154 };
0155
0156 - |
0157 // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
0158 // register offsets for DRV0 start at 01C00, the register calculations are
0159 // like this::
0160 // DRV0: 0xAF20000
0161 // TCS-OFFSET: 0x1C00
0162 #include <dt-bindings/interrupt-controller/arm-gic.h>
0163 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
0164
0165 rsc@af20000 {
0166 compatible = "qcom,rpmh-rsc";
0167 reg = <0xaf20000 0x10000>;
0168 reg-names = "drv-0";
0169 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
0170 label = "disp_rsc";
0171 qcom,tcs-offset = <0x1c00>;
0172 qcom,drv-id = <0>;
0173 qcom,tcs-config = <ACTIVE_TCS 0>,
0174 <SLEEP_TCS 1>,
0175 <WAKE_TCS 1>,
0176 <CONTROL_TCS 0>;
0177 };
0178
0179 - |
0180 #include <dt-bindings/interrupt-controller/arm-gic.h>
0181 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
0182 #include <dt-bindings/power/qcom-rpmpd.h>
0183
0184 rsc@18200000 {
0185 compatible = "qcom,rpmh-rsc";
0186 reg = <0x18200000 0x10000>,
0187 <0x18210000 0x10000>,
0188 <0x18220000 0x10000>;
0189 reg-names = "drv-0", "drv-1", "drv-2";
0190 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0191 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0192 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0193 label = "apps_rsc";
0194 qcom,tcs-offset = <0xd00>;
0195 qcom,drv-id = <2>;
0196 qcom,tcs-config = <ACTIVE_TCS 2>,
0197 <SLEEP_TCS 3>,
0198 <WAKE_TCS 3>,
0199 <CONTROL_TCS 0>;
0200
0201 clock-controller {
0202 compatible = "qcom,sm8350-rpmh-clk";
0203 #clock-cells = <1>;
0204 clock-names = "xo";
0205 clocks = <&xo_board>;
0206 };
0207
0208 power-controller {
0209 compatible = "qcom,sm8350-rpmhpd";
0210 #power-domain-cells = <1>;
0211 operating-points-v2 = <&rpmhpd_opp_table>;
0212
0213 rpmhpd_opp_table: opp-table {
0214 compatible = "operating-points-v2";
0215
0216 rpmhpd_opp_ret: opp1 {
0217 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
0218 };
0219
0220 rpmhpd_opp_min_svs: opp2 {
0221 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
0222 };
0223
0224 rpmhpd_opp_low_svs: opp3 {
0225 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
0226 };
0227
0228 rpmhpd_opp_svs: opp4 {
0229 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
0230 };
0231
0232 rpmhpd_opp_svs_l1: opp5 {
0233 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
0234 };
0235
0236 rpmhpd_opp_nom: opp6 {
0237 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
0238 };
0239
0240 rpmhpd_opp_nom_l1: opp7 {
0241 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
0242 };
0243
0244 rpmhpd_opp_nom_l2: opp8 {
0245 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
0246 };
0247
0248 rpmhpd_opp_turbo: opp9 {
0249 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
0250 };
0251
0252 rpmhpd_opp_turbo_l1: opp10 {
0253 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
0254 };
0255 };
0256 };
0257
0258 bcm-voter {
0259 compatible = "qcom,bcm-voter";
0260 };
0261 };
