0001 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm General Serial Bus Interface (GSBI)
0008
0009 maintainers:
0010 - Andy Gross <agross@kernel.org>
0011 - Bjorn Andersson <bjorn.andersson@linaro.org>
0012 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
0013
0014 description:
0015 The GSBI controller is modeled as a node with zero or more child nodes, each
0016 representing a serial sub-node device that is mux'd as part of the GSBI
0017 configuration settings. The mode setting will govern the input/output mode
0018 of the 4 GSBI IOs.
0019
0020 A GSBI controller node can contain 0 or more child nodes representing serial
0021 devices. These serial devices can be a QCOM UART, I2C controller, spi
0022 controller, or some combination of aforementioned devices.
0023
0024 properties:
0025 compatible:
0026 const: qcom,gsbi-v1.0.0
0027
0028 '#address-cells':
0029 const: 1
0030
0031 cell-index:
0032 $ref: /schemas/types.yaml#/definitions/uint32
0033 description:
0034 The GSBI index.
0035
0036 clocks:
0037 maxItems: 1
0038
0039 clock-names:
0040 const: iface
0041
0042 qcom,crci:
0043 $ref: /schemas/types.yaml#/definitions/uint32
0044 description:
0045 CRCI MUX value for QUP CRCI ports. Please reference
0046 include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
0047
0048 qcom,mode:
0049 $ref: /schemas/types.yaml#/definitions/uint32
0050 description:
0051 MUX value for configuration of the serial interface. Please reference
0052 include/dt-bindings/soc/qcom,gsbi.h for valid mux values.
0053
0054 '#size-cells':
0055 const: 1
0056
0057 syscon-tcsr:
0058 $ref: /schemas/types.yaml#/definitions/phandle
0059 description:
0060 Phandle of TCSR syscon node.Required if child uses dma.
0061
0062 ranges: true
0063
0064 reg:
0065 maxItems: 1
0066
0067 patternProperties:
0068 "spi@[0-9a-f]+$":
0069 type: object
0070 $ref: /schemas/spi/qcom,spi-qup.yaml#
0071
0072 "i2c@[0-9a-f]+$":
0073 type: object
0074 $ref: /schemas/i2c/qcom,i2c-qup.yaml#
0075
0076 "serial@[0-9a-f]+$":
0077 type: object
0078 $ref: /schemas/serial/qcom,msm-uartdm.yaml#
0079
0080 required:
0081 - compatible
0082 - cell-index
0083 - clocks
0084 - clock-names
0085 - qcom,mode
0086 - reg
0087
0088 additionalProperties: false
0089
0090 examples:
0091 - |
0092 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
0093 #include <dt-bindings/interrupt-controller/arm-gic.h>
0094 #include <dt-bindings/soc/qcom,gsbi.h>
0095
0096 gsbi@12440000 {
0097 compatible = "qcom,gsbi-v1.0.0";
0098 reg = <0x12440000 0x100>;
0099 cell-index = <1>;
0100 clocks = <&gcc GSBI1_H_CLK>;
0101 clock-names = "iface";
0102 #address-cells = <1>;
0103 #size-cells = <1>;
0104 ranges;
0105
0106 syscon-tcsr = <&tcsr>;
0107 qcom,mode = <GSBI_PROT_I2C_UART>;
0108
0109 serial@12450000 {
0110 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0111 reg = <0x12450000 0x100>,
0112 <0x12400000 0x03>;
0113 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
0114 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
0115 clock-names = "core", "iface";
0116 };
0117
0118 i2c@12460000 {
0119 compatible = "qcom,i2c-qup-v1.1.1";
0120 reg = <0x12460000 0x1000>;
0121 pinctrl-0 = <&i2c1_pins>;
0122 pinctrl-1 = <&i2c1_pins_sleep>;
0123 pinctrl-names = "default", "sleep";
0124 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
0125 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
0126 clock-names = "core", "iface";
0127 #address-cells = <1>;
0128 #size-cells = <0>;
0129
0130 status = "disabled"; /* UART chosen */
0131 };
0132 };
