0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: GENI Serial Engine QUP Wrapper Controller
0008
0009 maintainers:
0010 - Bjorn Andersson <bjorn.andersson@linaro.org>
0011
0012 description: |
0013 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
0014 is a programmable module for supporting a wide range of serial interfaces
0015 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
0016 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
0017 Wrapper controller is modeled as a node with zero or more child nodes each
0018 representing a serial engine.
0019
0020 properties:
0021 compatible:
0022 enum:
0023 - qcom,geni-se-qup
0024
0025 reg:
0026 description: QUP wrapper common register address and length.
0027 maxItems: 1
0028
0029 clock-names:
0030 items:
0031 - const: m-ahb
0032 - const: s-ahb
0033
0034 clocks:
0035 items:
0036 - description: Master AHB Clock
0037 - description: Slave AHB Clock
0038
0039 "#address-cells":
0040 const: 2
0041
0042 "#size-cells":
0043 const: 2
0044
0045 ranges: true
0046
0047 interconnects:
0048 maxItems: 1
0049
0050 interconnect-names:
0051 const: qup-core
0052
0053 iommus:
0054 maxItems: 1
0055
0056 required:
0057 - compatible
0058 - reg
0059 - clock-names
0060 - clocks
0061 - "#address-cells"
0062 - "#size-cells"
0063 - ranges
0064
0065 patternProperties:
0066 "spi@[0-9a-f]+$":
0067 type: object
0068 description: GENI serial engine based SPI controller. SPI in master mode
0069 supports up to 50MHz, up to four chip selects, programmable
0070 data path from 4 bits to 32 bits and numerous protocol
0071 variants.
0072 $ref: /schemas/spi/qcom,spi-geni-qcom.yaml#
0073
0074 "i2c@[0-9a-f]+$":
0075 type: object
0076 description: GENI serial engine based I2C controller.
0077 $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#
0078
0079 "serial@[0-9a-f]+$":
0080 type: object
0081 description: GENI Serial Engine based UART Controller.
0082 $ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
0083
0084 additionalProperties: false
0085
0086 examples:
0087 - |
0088 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
0089 #include <dt-bindings/interrupt-controller/arm-gic.h>
0090
0091 soc {
0092 #address-cells = <2>;
0093 #size-cells = <2>;
0094
0095 geniqup@8c0000 {
0096 compatible = "qcom,geni-se-qup";
0097 reg = <0 0x008c0000 0 0x6000>;
0098 clock-names = "m-ahb", "s-ahb";
0099 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
0100 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
0101 #address-cells = <2>;
0102 #size-cells = <2>;
0103 ranges;
0104
0105 i2c0: i2c@a94000 {
0106 compatible = "qcom,geni-i2c";
0107 reg = <0 0xa94000 0 0x4000>;
0108 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
0109 clock-names = "se";
0110 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
0111 pinctrl-names = "default", "sleep";
0112 pinctrl-0 = <&qup_1_i2c_5_active>;
0113 pinctrl-1 = <&qup_1_i2c_5_sleep>;
0114 #address-cells = <1>;
0115 #size-cells = <0>;
0116 };
0117
0118 uart0: serial@a88000 {
0119 compatible = "qcom,geni-uart";
0120 reg = <0 0xa88000 0 0x7000>;
0121 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
0122 clock-names = "se";
0123 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
0124 pinctrl-names = "default", "sleep";
0125 pinctrl-0 = <&qup_1_uart_3_active>;
0126 pinctrl-1 = <&qup_1_uart_3_sleep>;
0127 };
0128 };
0129 };
0130
0131 ...
