0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Always-On Subsystem side channel binding
0008
0009 maintainers:
0010 - Bjorn Andersson <bjorn.andersson@linaro.org>
0011
0012 description:
0013 This binding describes the hardware component responsible for side channel
0014 requests to the always-on subsystem (AOSS), used for certain power management
0015 requests that is not handled by the standard RPMh interface. Each client in the
0016 SoC has its own block of message RAM and IRQ for communication with the AOSS.
0017 The protocol used to communicate in the message RAM is known as Qualcomm
0018 Messaging Protocol (QMP)
0019
0020 The AOSS side channel exposes control over a set of resources, used to control
0021 a set of debug related clocks and to affect the low power state of resources
0022 related to the secondary subsystems.
0023
0024 properties:
0025 compatible:
0026 items:
0027 - enum:
0028 - qcom,sc7180-aoss-qmp
0029 - qcom,sc7280-aoss-qmp
0030 - qcom,sc8180x-aoss-qmp
0031 - qcom,sdm845-aoss-qmp
0032 - qcom,sm6350-aoss-qmp
0033 - qcom,sm8150-aoss-qmp
0034 - qcom,sm8250-aoss-qmp
0035 - qcom,sm8350-aoss-qmp
0036 - qcom,sm8450-aoss-qmp
0037 - const: qcom,aoss-qmp
0038
0039 reg:
0040 maxItems: 1
0041 description:
0042 The base address and size of the message RAM for this client's
0043 communication with the AOSS
0044
0045 interrupts:
0046 maxItems: 1
0047 description:
0048 Should specify the AOSS message IRQ for this client
0049
0050 mboxes:
0051 maxItems: 1
0052 description:
0053 Reference to the mailbox representing the outgoing doorbell in APCS for
0054 this client, as described in mailbox/mailbox.txt
0055
0056 "#clock-cells":
0057 const: 0
0058 description:
0059 The single clock represents the QDSS clock.
0060
0061 required:
0062 - compatible
0063 - reg
0064 - interrupts
0065 - mboxes
0066 - "#clock-cells"
0067
0068 additionalProperties: false
0069
0070 patternProperties:
0071 "^(cx|mx|ebi)$":
0072 type: object
0073 description:
0074 The AOSS side channel also provides the controls for three cooling devices,
0075 these are expressed as subnodes of the QMP node. The name of the node is
0076 used to identify the resource and must therefor be "cx", "mx" or "ebi".
0077
0078 properties:
0079 "#cooling-cells":
0080 const: 2
0081
0082 required:
0083 - "#cooling-cells"
0084
0085 additionalProperties: false
0086
0087 examples:
0088 - |
0089 #include <dt-bindings/interrupt-controller/arm-gic.h>
0090
0091 aoss_qmp: qmp@c300000 {
0092 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
0093 reg = <0x0c300000 0x100000>;
0094 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
0095 mboxes = <&apss_shared 0>;
0096
0097 #clock-cells = <0>;
0098
0099 cx_cdev: cx {
0100 #cooling-cells = <2>;
0101 };
0102
0103 mx_cdev: mx {
0104 #cooling-cells = <2>;
0105 };
0106 };
0107 ...
