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0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: MediaTek Smart Voltage Scaling (SVS) Device Tree Bindings
0008 
0009 maintainers:
0010   - Roger Lu <roger.lu@mediatek.com>
0011   - Matthias Brugger <matthias.bgg@gmail.com>
0012   - Kevin Hilman <khilman@kernel.org>
0013 
0014 description: |+
0015   The SVS engine is a piece of hardware which has several
0016   controllers(banks) for calculating suitable voltage to
0017   different power domains(CPU/GPU/CCI) according to
0018   chip process corner, temperatures and other factors. Then DVFS
0019   driver could apply SVS bank voltage to PMIC/Buck.
0020 
0021 properties:
0022   compatible:
0023     enum:
0024       - mediatek,mt8183-svs
0025       - mediatek,mt8192-svs
0026 
0027   reg:
0028     maxItems: 1
0029     description: Address range of the MTK SVS controller.
0030 
0031   interrupts:
0032     maxItems: 1
0033 
0034   clocks:
0035     maxItems: 1
0036     description: Main clock for MTK SVS controller to work.
0037 
0038   clock-names:
0039     const: main
0040 
0041   nvmem-cells:
0042     minItems: 1
0043     description:
0044       Phandle to the calibration data provided by a nvmem device.
0045     items:
0046       - description: SVS efuse for SVS controller
0047       - description: Thermal efuse for SVS controller
0048 
0049   nvmem-cell-names:
0050     items:
0051       - const: svs-calibration-data
0052       - const: t-calibration-data
0053 
0054   resets:
0055     maxItems: 1
0056 
0057   reset-names:
0058     items:
0059       - const: svs_rst
0060 
0061 required:
0062   - compatible
0063   - reg
0064   - interrupts
0065   - clocks
0066   - clock-names
0067   - nvmem-cells
0068   - nvmem-cell-names
0069 
0070 additionalProperties: false
0071 
0072 examples:
0073   - |
0074     #include <dt-bindings/clock/mt8183-clk.h>
0075     #include <dt-bindings/interrupt-controller/arm-gic.h>
0076     #include <dt-bindings/interrupt-controller/irq.h>
0077 
0078     soc {
0079         #address-cells = <2>;
0080         #size-cells = <2>;
0081 
0082         svs@1100b000 {
0083             compatible = "mediatek,mt8183-svs";
0084             reg = <0 0x1100b000 0 0x1000>;
0085             interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
0086             clocks = <&infracfg CLK_INFRA_THERM>;
0087             clock-names = "main";
0088             nvmem-cells = <&svs_calibration>, <&thermal_calibration>;
0089             nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
0090         };
0091     };