soc/mediatek/mediatek%2Cmutex.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek mutex
0008
0009 maintainers:
0010   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011   - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014   Mediatek mutex, namely MUTEX, is used to send the triggers signals called
0015   Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
0016   data path or MDP data path.
0017   In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
0018   the shadow register.
0019   MUTEX device node must be siblings to the central MMSYS_CONFIG node.
0020   For a description of the MMSYS_CONFIG binding, see
0021   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
0022   for details.
0023
0024 properties:
0025   compatible:
0026     enum:
0027       - mediatek,mt2701-disp-mutex
0028       - mediatek,mt2712-disp-mutex
0029       - mediatek,mt8167-disp-mutex
0030       - mediatek,mt8173-disp-mutex
0031       - mediatek,mt8183-disp-mutex
0032       - mediatek,mt8186-disp-mutex
0033       - mediatek,mt8192-disp-mutex
0034       - mediatek,mt8195-disp-mutex
0035
0036   reg:
0037     maxItems: 1
0038
0039   interrupts:
0040     maxItems: 1
0041
0042   power-domains:
0043     description: A phandle and PM domain specifier as defined by bindings of
0044       the power controller specified by phandle. See
0045       Documentation/devicetree/bindings/power/power-domain.yaml for details.
0046
0047   clocks:
0048     items:
0049       - description: MUTEX Clock
0050
0051   mediatek,gce-events:
0052     description:
0053       The event id which is mapping to the specific hardware event signal
0054       to gce. The event id is defined in the gce header
0055       include/dt-bindings/gce/<chip>-gce.h of each chips.
0056     $ref: /schemas/types.yaml#/definitions/uint32-array
0057
0058   mediatek,gce-client-reg:
0059     $ref: /schemas/types.yaml#/definitions/phandle-array
0060     items:
0061       items:
0062         - description: phandle of GCE
0063         - description: GCE subsys id
0064         - description: register offset
0065         - description: register size
0066     description: The register of client driver can be configured by gce with
0067       4 arguments defined in this property. Each GCE subsys id is mapping to
0068       a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
0069
0070 required:
0071   - compatible
0072   - reg
0073   - interrupts
0074   - power-domains
0075   - clocks
0076
0077 additionalProperties: false
0078
0079 examples:
0080   - |
0081     #include <dt-bindings/interrupt-controller/arm-gic.h>
0082     #include <dt-bindings/clock/mt8173-clk.h>
0083     #include <dt-bindings/power/mt8173-power.h>
0084     #include <dt-bindings/gce/mt8173-gce.h>
0085
0086     soc {
0087         #address-cells = <2>;
0088         #size-cells = <2>;
0089
0090         mutex: mutex@14020000 {
0091             compatible = "mediatek,mt8173-disp-mutex";
0092             reg = <0 0x14020000 0 0x1000>;
0093             interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
0094             power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
0095             clocks = <&mmsys CLK_MM_MUTEX_32K>;
0096             mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
0097                                   <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
0098         };
0099     };