0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP i.MX8MP Media Block Control
0008
0009 maintainers:
0010 - Paul Elder <paul.elder@ideasonboard.com>
0011
0012 description:
0013 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
0014 providing access to the NoC and ensuring proper power sequencing of the
0015 peripherals within the MEDIAMIX domain.
0016
0017 properties:
0018 compatible:
0019 items:
0020 - const: fsl,imx8mp-media-blk-ctrl
0021 - const: syscon
0022
0023 reg:
0024 maxItems: 1
0025
0026 '#power-domain-cells':
0027 const: 1
0028
0029 power-domains:
0030 maxItems: 10
0031
0032 power-domain-names:
0033 items:
0034 - const: bus
0035 - const: mipi-dsi1
0036 - const: mipi-csi1
0037 - const: lcdif1
0038 - const: isi
0039 - const: mipi-csi2
0040 - const: lcdif2
0041 - const: isp
0042 - const: dwe
0043 - const: mipi-dsi2
0044
0045 clocks:
0046 items:
0047 - description: The APB clock
0048 - description: The AXI clock
0049 - description: The pixel clock for the first CSI2 receiver (aclk)
0050 - description: The pixel clock for the second CSI2 receiver (aclk)
0051 - description: The pixel clock for the first LCDIF (pix_clk)
0052 - description: The pixel clock for the second LCDIF (pix_clk)
0053 - description: The core clock for the ISP (clk)
0054 - description: The MIPI-PHY reference clock used by DSI
0055
0056 clock-names:
0057 items:
0058 - const: apb
0059 - const: axi
0060 - const: cam1
0061 - const: cam2
0062 - const: disp1
0063 - const: disp2
0064 - const: isp
0065 - const: phy
0066
0067 required:
0068 - compatible
0069 - reg
0070 - '#power-domain-cells'
0071 - power-domains
0072 - power-domain-names
0073 - clocks
0074 - clock-names
0075
0076 additionalProperties: false
0077
0078 examples:
0079 - |
0080 #include <dt-bindings/clock/imx8mp-clock.h>
0081 #include <dt-bindings/power/imx8mp-power.h>
0082
0083 media_blk_ctl: blk-ctl@32ec0000 {
0084 compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
0085 reg = <0x32ec0000 0x138>;
0086 power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
0087 <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
0088 <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
0089 <&mipi_phy2_pd>;
0090 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
0091 "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2";
0092 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
0093 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
0094 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
0095 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
0096 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
0097 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
0098 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
0099 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
0100 clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
0101 "isp", "phy";
0102 #power-domain-cells = <1>;
0103 };
0104 ...
