0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP i.MX8MM DISP blk-ctrl
0008
0009 maintainers:
0010 - Lucas Stach <l.stach@pengutronix.de>
0011
0012 description:
0013 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
0014 the NoC and ensuring proper power sequencing of the display and MIPI CSI
0015 peripherals located in the DISP domain of the SoC.
0016
0017 properties:
0018 compatible:
0019 items:
0020 - const: fsl,imx8mm-disp-blk-ctrl
0021 - const: syscon
0022
0023 reg:
0024 maxItems: 1
0025
0026 '#power-domain-cells':
0027 const: 1
0028
0029 power-domains:
0030 minItems: 5
0031 maxItems: 5
0032
0033 power-domain-names:
0034 items:
0035 - const: bus
0036 - const: csi-bridge
0037 - const: lcdif
0038 - const: mipi-dsi
0039 - const: mipi-csi
0040
0041 clocks:
0042 minItems: 10
0043 maxItems: 10
0044
0045 clock-names:
0046 items:
0047 - const: csi-bridge-axi
0048 - const: csi-bridge-apb
0049 - const: csi-bridge-core
0050 - const: lcdif-axi
0051 - const: lcdif-apb
0052 - const: lcdif-pix
0053 - const: dsi-pclk
0054 - const: dsi-ref
0055 - const: csi-aclk
0056 - const: csi-pclk
0057
0058 required:
0059 - compatible
0060 - reg
0061 - power-domains
0062 - power-domain-names
0063 - clocks
0064 - clock-names
0065
0066 additionalProperties: false
0067
0068 examples:
0069 - |
0070 #include <dt-bindings/clock/imx8mm-clock.h>
0071 #include <dt-bindings/power/imx8mm-power.h>
0072
0073 disp_blk_ctl: blk_ctrl@32e28000 {
0074 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
0075 reg = <0x32e28000 0x100>;
0076 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>,
0077 <&pgc_mipi>, <&pgc_mipi>;
0078 power-domain-names = "bus", "csi-bridge", "lcdif",
0079 "mipi-dsi", "mipi-csi";
0080 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
0081 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
0082 <&clk IMX8MM_CLK_CSI1_ROOT>,
0083 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
0084 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
0085 <&clk IMX8MM_CLK_DISP_ROOT>,
0086 <&clk IMX8MM_CLK_DSI_CORE>,
0087 <&clk IMX8MM_CLK_DSI_PHY_REF>,
0088 <&clk IMX8MM_CLK_CSI1_CORE>,
0089 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
0090 clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core",
0091 "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
0092 "dsi-ref", "csi-aclk", "csi-pclk";
0093 #power-domain-cells = <1>;
0094 };
