0001 * Run Control and Power Management
0002 -------------------------------------------
0003 The RCPM performs all device-level tasks associated with device run control
0004 and power management.
0005
0006 Required properites:
0007 - reg : Offset and length of the register set of the RCPM block.
0008 - #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
0009 fsl,rcpm-wakeup property.
0010 - compatible : Must contain a chip-specific RCPM block compatible string
0011 and (if applicable) may contain a chassis-version RCPM compatible
0012 string. Chip-specific strings are of the form "fsl,<chip>-rcpm",
0013 such as:
0014 * "fsl,p2041-rcpm"
0015 * "fsl,p5020-rcpm"
0016 * "fsl,t4240-rcpm"
0017
0018 Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>",
0019 such as:
0020 * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
0021 * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
0022 * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
0023 * "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm
0024
0025 All references to "1.0" and "2.0" refer to the QorIQ chassis version to
0026 which the chip complies.
0027 Chassis Version Example Chips
0028 --------------- -------------------------------
0029 1.0 p4080, p5020, p5040, p2041, p3041
0030 2.0 t4240, b4860, b4420
0031 2.1 t1040,
0032 2.1+ ls1021a, ls1012a, ls1043a, ls1046a
0033
0034 Optional properties:
0035 - little-endian : RCPM register block is Little Endian. Without it RCPM
0036 will be Big Endian (default case).
0037
0038 Example:
0039 The RCPM node for T4240:
0040 rcpm: global-utilities@e2000 {
0041 compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
0042 reg = <0xe2000 0x1000>;
0043 #fsl,rcpm-wakeup-cells = <2>;
0044 };
0045
0046 * Freescale RCPM Wakeup Source Device Tree Bindings
0047 -------------------------------------------
0048 Required fsl,rcpm-wakeup property should be added to a device node if the device
0049 can be used as a wakeup source.
0050
0051 - fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR
0052 register cells. The number of IPPDEXPCR register cells is defined in
0053 "#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is
0054 the bit mask that should be set in IPPDEXPCR0, and the second register
0055 cell is for IPPDEXPCR1, and so on.
0056
0057 Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a
0058 mechanism for keeping certain blocks awake during STANDBY and MEM, in
0059 order to use them as wake-up sources.
0060
0061 Example:
0062 lpuart0: serial@2950000 {
0063 compatible = "fsl,ls1021a-lpuart";
0064 reg = <0x0 0x2950000 0x0 0x1000>;
0065 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0066 clocks = <&sysclk>;
0067 clock-names = "ipg";
0068 fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>;
0069 };
