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OSCL-LXR

 
 

    


0001 * VIA VT8500 and WonderMedia WM8xxx UART Controller
0002 
0003 Required properties:
0004 - compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
0005         including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
0006 
0007 - reg: base physical address of the controller and length of memory mapped
0008         region.
0009 
0010 - interrupts: hardware interrupt number
0011 
0012 - clocks: shall be the input parent clock phandle for the clock. This should
0013         be the 24Mhz reference clock.
0014 
0015 Aliases may be defined to ensure the correct ordering of the uarts.
0016 
0017 Example:
0018         aliases {
0019                 serial0 = &uart0;
0020         };
0021 
0022         uart0: serial@d8200000 {
0023                 compatible = "via,vt8500-uart";
0024                 reg = <0xd8200000 0x1040>;
0025                 interrupts = <32>;
0026                 clocks = <&clkuart0>;
0027         };