0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: SiFive asynchronous serial interface (UART)
0008
0009 maintainers:
0010 - Pragnesh Patel <pragnesh.patel@sifive.com>
0011 - Paul Walmsley <paul.walmsley@sifive.com>
0012 - Palmer Dabbelt <palmer@sifive.com>
0013
0014 allOf:
0015 - $ref: serial.yaml#
0016
0017 properties:
0018 compatible:
0019 items:
0020 - enum:
0021 - sifive,fu540-c000-uart
0022 - sifive,fu740-c000-uart
0023 - canaan,k210-uarths
0024 - const: sifive,uart0
0025
0026 description:
0027 Should be something similar to "sifive,<chip>-uart"
0028 for the UART as integrated on a particular chip,
0029 and "sifive,uart<version>" for the general UART IP
0030 block programming model.
0031
0032 UART HDL that corresponds to the IP block version
0033 numbers can be found here -
0034
0035 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
0036
0037 reg:
0038 maxItems: 1
0039
0040 interrupts:
0041 maxItems: 1
0042
0043 clocks:
0044 maxItems: 1
0045
0046 required:
0047 - compatible
0048 - reg
0049 - interrupts
0050 - clocks
0051
0052 unevaluatedProperties: false
0053
0054 examples:
0055 - |
0056 #include <dt-bindings/clock/sifive-fu540-prci.h>
0057 serial@10010000 {
0058 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
0059 interrupt-parent = <&plic0>;
0060 interrupts = <80>;
0061 reg = <0x10010000 0x1000>;
0062 clocks = <&prci FU540_PRCI_CLK_TLCLK>;
0063 };
0064
0065 ...
