0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Qualcomm Geni based QUP UART interface
0008
0009 maintainers:
0010 - Andy Gross <agross@kernel.org>
0011 - Bjorn Andersson <bjorn.andersson@linaro.org>
0012
0013 allOf:
0014 - $ref: /schemas/serial/serial.yaml#
0015
0016 properties:
0017 compatible:
0018 enum:
0019 - qcom,geni-uart
0020 - qcom,geni-debug-uart
0021
0022 clocks:
0023 maxItems: 1
0024
0025 clock-names:
0026 const: se
0027
0028 interconnects:
0029 maxItems: 2
0030
0031 interconnect-names:
0032 items:
0033 - const: qup-core
0034 - const: qup-config
0035
0036 interrupts:
0037 minItems: 1
0038 items:
0039 - description: UART core irq
0040 - description: Wakeup irq (RX GPIO)
0041
0042 operating-points-v2: true
0043
0044 pinctrl-0: true
0045 pinctrl-1: true
0046
0047 pinctrl-names:
0048 minItems: 1
0049 items:
0050 - const: default
0051 - const: sleep
0052
0053 power-domains:
0054 maxItems: 1
0055
0056 reg:
0057 maxItems: 1
0058
0059 required:
0060 - compatible
0061 - clocks
0062 - clock-names
0063 - interrupts
0064 - reg
0065
0066 unevaluatedProperties: false
0067
0068 examples:
0069 - |
0070 #include <dt-bindings/interrupt-controller/arm-gic.h>
0071 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
0072 #include <dt-bindings/interconnect/qcom,sc7180.h>
0073
0074 serial@a88000 {
0075 compatible = "qcom,geni-uart";
0076 reg = <0xa88000 0x7000>;
0077 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
0078 clock-names = "se";
0079 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
0080 pinctrl-0 = <&qup_uart0_default>;
0081 pinctrl-names = "default";
0082 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
0083 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
0084 interconnect-names = "qup-core", "qup-config";
0085 };
0086 ...
